130 lines
2.5 KiB
C
130 lines
2.5 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief interrupt management code for riscv SOCs supporting the riscv
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privileged architecture specification
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*/
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#include <zephyr/irq.h>
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#include <zephyr/irq_multilevel.h>
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#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
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#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
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#if defined(CONFIG_RISCV_HAS_CLIC)
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void arch_irq_enable(unsigned int irq)
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{
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riscv_clic_irq_enable(irq);
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}
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void arch_irq_disable(unsigned int irq)
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{
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riscv_clic_irq_disable(irq);
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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return riscv_clic_irq_is_enabled(irq);
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}
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void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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riscv_clic_irq_priority_set(irq, prio, flags);
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}
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void z_riscv_irq_vector_set(unsigned int irq)
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{
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#if defined(CONFIG_CLIC_SMCLICSHV_EXT)
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riscv_clic_irq_vector_set(irq);
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#else
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ARG_UNUSED(irq);
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#endif
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}
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#else /* PLIC + HLINT/CLINT or HLINT/CLINT only */
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void arch_irq_enable(unsigned int irq)
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{
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uint32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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unsigned int level = irq_get_level(irq);
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if (level == 2) {
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riscv_plic_irq_enable(irq);
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return;
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}
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#endif
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/*
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* CSR mie register is updated using atomic instruction csrrs
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* (atomic read and set bits in CSR register)
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*/
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mie = csr_read_set(mie, 1 << irq);
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}
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void arch_irq_disable(unsigned int irq)
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{
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uint32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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unsigned int level = irq_get_level(irq);
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if (level == 2) {
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riscv_plic_irq_disable(irq);
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return;
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}
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#endif
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/*
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* Use atomic instruction csrrc to disable device interrupt in mie CSR.
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* (atomic read and clear bits in CSR register)
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*/
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mie = csr_read_clear(mie, 1 << irq);
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}
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int arch_irq_is_enabled(unsigned int irq)
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{
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uint32_t mie;
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#if defined(CONFIG_RISCV_HAS_PLIC)
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unsigned int level = irq_get_level(irq);
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if (level == 2) {
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return riscv_plic_irq_is_enabled(irq);
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}
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#endif
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mie = csr_read(mie);
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return !!(mie & (1 << irq));
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}
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#if defined(CONFIG_RISCV_HAS_PLIC)
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void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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unsigned int level = irq_get_level(irq);
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if (level == 2) {
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riscv_plic_set_priority(irq, prio);
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}
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}
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#endif /* CONFIG_RISCV_HAS_PLIC */
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#endif /* CONFIG_RISCV_HAS_CLIC */
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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__weak void soc_interrupt_init(void)
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{
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/* ensure that all interrupts are disabled */
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(void)arch_irq_lock();
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csr_write(mie, 0);
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csr_write(mip, 0);
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}
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#endif
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