185 lines
3.9 KiB
C
185 lines
3.9 KiB
C
/*
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* Copyright (c) 2016 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SPI_SPI_LL_STM32_H_
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#define ZEPHYR_DRIVERS_SPI_SPI_LL_STM32_H_
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#include "spi_context.h"
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typedef void (*irq_config_func_t)(const struct device *port);
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struct spi_stm32_config {
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struct stm32_pclken pclken;
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SPI_TypeDef *spi;
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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irq_config_func_t irq_config;
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#endif
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};
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#ifdef CONFIG_SPI_STM32_DMA
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struct stream {
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const char *dma_name;
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uint32_t channel; /* stores the channel for dma or mux */
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struct dma_config dma_cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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bool transfer_complete;
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int fifo_threshold;
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};
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#endif
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struct spi_stm32_data {
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struct spi_context ctx;
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#ifdef CONFIG_SPI_STM32_DMA
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const struct device *dev_dma_tx;
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const struct device *dev_dma_rx;
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struct stream dma_rx;
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struct stream dma_tx;
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size_t dma_segment_len;
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#endif
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};
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static inline uint32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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return LL_SPI_IsActiveFlag_TXP(spi);
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#else
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return LL_SPI_IsActiveFlag_TXE(spi);
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#endif
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}
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static inline uint32_t ll_func_rx_is_not_empty(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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return LL_SPI_IsActiveFlag_RXP(spi);
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#else
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return LL_SPI_IsActiveFlag_RXNE(spi);
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#endif
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}
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static inline void ll_func_enable_int_tx_empty(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_EnableIT_TXP(spi);
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#else
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LL_SPI_EnableIT_TXE(spi);
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#endif
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}
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static inline void ll_func_enable_int_rx_not_empty(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_EnableIT_RXP(spi);
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#else
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LL_SPI_EnableIT_RXNE(spi);
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#endif
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}
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static inline void ll_func_enable_int_errors(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_EnableIT_UDR(spi);
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LL_SPI_EnableIT_OVR(spi);
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LL_SPI_EnableIT_CRCERR(spi);
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LL_SPI_EnableIT_FRE(spi);
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LL_SPI_EnableIT_MODF(spi);
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#else
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LL_SPI_EnableIT_ERR(spi);
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#endif
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}
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static inline void ll_func_disable_int_tx_empty(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_DisableIT_TXP(spi);
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#else
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LL_SPI_DisableIT_TXE(spi);
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#endif
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}
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static inline void ll_func_disable_int_rx_not_empty(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_DisableIT_RXP(spi);
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#else
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LL_SPI_DisableIT_RXNE(spi);
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#endif
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}
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static inline void ll_func_disable_int_errors(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_DisableIT_UDR(spi);
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LL_SPI_DisableIT_OVR(spi);
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LL_SPI_DisableIT_CRCERR(spi);
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LL_SPI_DisableIT_FRE(spi);
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LL_SPI_DisableIT_MODF(spi);
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#else
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LL_SPI_DisableIT_ERR(spi);
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#endif
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}
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static inline uint32_t ll_func_spi_is_busy(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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return (!LL_SPI_IsActiveFlag_MODF(spi) &&
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!LL_SPI_IsActiveFlag_TXC(spi));
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#else
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return LL_SPI_IsActiveFlag_BSY(spi);
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#endif
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}
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/* Header is compiled first, this switch avoid the compiler to lookup for
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* non-existing LL FIFO functions for SoC without SPI FIFO
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*/
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_fifo)
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static inline void ll_func_set_fifo_threshold_8bit(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_01DATA);
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#else
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LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
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#endif
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}
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static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_02DATA);
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#else
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LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_HALF);
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#endif
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}
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#endif
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static inline void ll_func_disable_spi(SPI_TypeDef *spi)
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{
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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if (LL_SPI_IsActiveMasterTransfer(spi)) {
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LL_SPI_SuspendMasterTransfer(spi);
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while (LL_SPI_IsActiveMasterTransfer(spi)) {
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/* NOP */
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}
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}
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LL_SPI_Disable(spi);
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while (LL_SPI_IsEnabled(spi)) {
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/* NOP */
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}
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/* Flush RX buffer */
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while (LL_SPI_IsActiveFlag_RXP(spi)) {
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(void)LL_SPI_ReceiveData8(spi);
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}
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LL_SPI_ClearFlag_SUSP(spi);
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#else
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LL_SPI_Disable(spi);
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#endif
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}
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#endif /* ZEPHYR_DRIVERS_SPI_SPI_LL_STM32_H_ */
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