620 lines
16 KiB
C
620 lines
16 KiB
C
/*
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* Copyright (c) 2020 Seagate Technology LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc11u6x_gpio
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/**
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* @file
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* @brief GPIO driver for NXP LPC11U6X SoCs
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*
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* This driver allows to configure the GPIOs found on the LPC11U6x MCUs.
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*
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* @note See the UM10732 LPC11U6x/E6x user manual for register definitions.
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*/
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#include <drivers/clock_control.h>
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#include <drivers/gpio.h>
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#include <drivers/pinmux.h>
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#include <dt-bindings/pinctrl/lpc11u6x-pinctrl.h>
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#include "gpio_utils.h"
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#define DEV_CFG(dev) ((const struct gpio_lpc11u6x_config *) \
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((dev)->config))
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#define DEV_DATA(dev) ((struct gpio_lpc11u6x_data *) \
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((dev)->data))
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/* Offset from syscon base address. */
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#define LPC11U6X_PINTSEL_REGS 0x178
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/* Offsets from GPIO base address. */
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#define LPC11U6X_GPIO_REGS 0x2000
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#define LPC11U6X_PINT_REGS 0x4000
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/**
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* @brief Structure mapping the GPIO registers.
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*
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* @note The byte and word pin registers are not included because they are
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* not used by this driver. A 0x2000 offset is applied to skip them.
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*/
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struct lpc11u6x_gpio_regs {
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volatile uint32_t dir[3];
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volatile uint32_t _unused1[29];
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volatile uint32_t mask[3];
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volatile uint32_t _unused2[29];
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volatile uint32_t pin[3];
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volatile uint32_t _unused3[29];
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volatile uint32_t mpin[3];
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volatile uint32_t _unused4[29];
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volatile uint32_t set[3];
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volatile uint32_t _unused5[29];
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volatile uint32_t clr[3];
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volatile uint32_t _unused6[29];
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volatile uint32_t not[3];
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};
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/**
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* @brief Structure mapping the PINT registers.
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*/
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struct lpc11u6x_pint_regs {
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volatile uint32_t isel;
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volatile uint32_t ienr;
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volatile uint32_t sienr;
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volatile uint32_t cienr;
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volatile uint32_t ienf;
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volatile uint32_t sienf;
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volatile uint32_t cienf;
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volatile uint32_t rise;
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volatile uint32_t fall;
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volatile uint32_t ist;
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volatile uint32_t pmctrl;
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volatile uint32_t pmsrc;
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volatile uint32_t pmcfg;
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};
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/**
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* @brief Structure for resources and information shared between GPIO ports.
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*
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* This structure is included by all the per-port private configuration.
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* It gathers all the resources and information shared between all the GPIO
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* ports: GPIO and SYSCON registers base addresses, clock name and subsystem.
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*/
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struct gpio_lpc11u6x_shared {
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char *clock_controller_name;
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clock_control_subsys_t clock_subsys;
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uint32_t gpio_base;
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uint32_t syscon_base;
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uint8_t nirqs;
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};
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struct gpio_lpc11u6x_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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const struct gpio_lpc11u6x_shared *shared;
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char *pinmux_name;
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uint8_t port_num;
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uint8_t ngpios;
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};
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struct gpio_lpc11u6x_data {
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/* gpio_driver_data needs to be first. */
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struct gpio_driver_data common;
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const struct device *pinmux_dev;
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sys_slist_t cb_list;
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};
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static int gpio_lpc11u6x_pin_configure(const struct device *port,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct gpio_lpc11u6x_data *data = DEV_DATA(port);
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struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
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(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
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uint8_t port_num = config->port_num;
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uint32_t func;
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int ret;
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if (pin >= config->ngpios) {
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return -EINVAL;
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}
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/*
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* PIO0_4 and PIO0_5 are "true" open drain pins muxed with the I2C port
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* 0. They still can be configured as GPIOs but only in open drain mode
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* and with no pull-down or pull-up resitor enabled.
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*/
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if (port_num == 0 && (pin == 4 || pin == 5) &&
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((flags & GPIO_OPEN_DRAIN) == 0 ||
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(flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)))) {
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return -EINVAL;
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}
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/*
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* For PIO0_0 and PIO0_[10-15] function 1 enables GPIO mode. For all
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* the other pins, function 0 must be selected.
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*/
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if (port_num == 0 && (pin == 0 || (pin >= 10 && pin <= 15))) {
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func = IOCON_FUNC1;
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} else {
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func = IOCON_FUNC0;
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}
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if (flags & GPIO_SINGLE_ENDED) {
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/* Open source mode is not supported. */
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if (flags & GPIO_LINE_OPEN_DRAIN)
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func |= IOCON_OPENDRAIN_EN;
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else
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return -ENOTSUP;
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}
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if (flags & GPIO_PULL_UP) {
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func |= IOCON_MODE_PULLUP;
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} else if (flags & GPIO_PULL_DOWN) {
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func |= IOCON_MODE_PULLDOWN;
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} else {
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func |= IOCON_MODE_INACT;
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}
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ret = pinmux_pin_set(data->pinmux_dev, pin, func);
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if (ret < 0) {
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return ret;
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}
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/* Initial output value. */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_regs->set[port_num] |= BIT(pin);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_regs->clr[port_num] |= BIT(pin);
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}
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/*
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* TODO: maybe configure the STARTERP0 register to allow wake-up from
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* deep-sleep or power-down modes.
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*/
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/* Configure GPIO direction. */
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WRITE_BIT(gpio_regs->dir[port_num], pin, flags & GPIO_OUTPUT);
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return 0;
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}
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static int gpio_lpc11u6x_port_get_raw(const struct device *port,
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gpio_port_value_t *value)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
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(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
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*value = gpio_regs->pin[config->port_num];
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return 0;
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}
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static int gpio_lpc11u6x_port_set_masked_raw(const struct device *port,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
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(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
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uint8_t port_num = config->port_num;
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uint32_t orig_mask;
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orig_mask = gpio_regs->mask[port_num];
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/* Apply inverted mask (bit set to 1 masks the pin). */
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gpio_regs->mask[port_num] = ~mask;
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compiler_barrier();
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/* Update pins values. */
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gpio_regs->mpin[port_num] = value;
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compiler_barrier();
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/* Restore original mask. */
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gpio_regs->mask[port_num] = orig_mask;
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compiler_barrier();
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return 0;
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}
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static int gpio_lpc11u6x_port_set_bits_raw(const struct device *port,
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gpio_port_pins_t pins)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
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(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
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gpio_regs->set[config->port_num] = pins;
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return 0;
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}
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static int gpio_lpc11u6x_port_clear_bits_raw(const struct device *port,
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gpio_port_pins_t pins)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
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(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
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gpio_regs->clr[config->port_num] = pins;
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return 0;
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}
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static int gpio_lpc11u6x_port_toggle_bits(const struct device *port,
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gpio_port_pins_t pins)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
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(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
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gpio_regs->not[config->port_num] = pins;
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return 0;
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}
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/**
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* @brief Attach a free interrupt line to a GPIO.
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*
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* @param shared Pointer to a structure shared between all the GPIO ports.
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* @param intpin GPIO port and pin numbers encoded into a value compatible
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* with the INTPIN register (included in the PINTSEL register).
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*
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* @retval >0 Number of the attached interrupt on success.
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* @retval -EBUSY All the interrupt lines are already attached.
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*/
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static int
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pintsel_attach(const struct gpio_lpc11u6x_shared *shared, uint8_t intpin)
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{
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uint8_t irq;
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int ret = -EBUSY;
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uint32_t *pintsel_reg =
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(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);
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for (irq = 0; irq < shared->nirqs; irq++) {
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/* GPIO already attached. */
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if ((pintsel_reg[irq] & BIT_MASK(5)) == intpin) {
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return irq;
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}
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if (ret < 0 && (pintsel_reg[irq] & BIT_MASK(5)) == 0) {
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ret = irq;
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}
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}
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/* Attach GPIO to the first free interrupt found if any. */
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if (ret >= 0) {
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pintsel_reg[ret] = intpin;
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}
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return ret;
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}
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/**
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* @brief Detach an interrupt line from a GPIO.
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*
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* @param shared Pointer to a structure shared between all the GPIO ports.
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* @param intpin GPIO port and pin numbers encoded into a value compatible
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* with the INTPIN register (included in the PINTSEL register).
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*
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* @retval >0 Number of the detached interrupt on success.
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* @retval -EINVAL No attached interrupt found for the requested GPIO.
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*/
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static int
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pintsel_detach(const struct gpio_lpc11u6x_shared *shared, uint8_t intpin)
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{
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uint8_t irq;
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uint32_t *pintsel_reg =
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(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);
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for (irq = 0; irq < shared->nirqs; irq++) {
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if ((pintsel_reg[irq] & BIT_MASK(5)) == intpin) {
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pintsel_reg[irq] = 0;
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return irq;
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}
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}
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return -EINVAL;
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}
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static int gpio_lpc11u6x_pin_interrupt_configure(const struct device *port,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_lpc11u6x_config *config = DEV_CFG(port);
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struct lpc11u6x_pint_regs *pint_regs = (struct lpc11u6x_pint_regs *)
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(config->shared->gpio_base + LPC11U6X_PINT_REGS);
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uint8_t intpin;
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int irq;
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if (pin >= config->ngpios) {
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return -EINVAL;
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}
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/*
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* Because the PINTSEL register only have 6 bits to encode a pin
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* number, then PIO2_8 to PIO2_23 can't be attacehd to an interrupt
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* line.
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*/
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if (config->port_num == 2 && pin > 7) {
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return -ENOTSUP;
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}
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/*
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* Convert the requested GPIO port and pin numbers into a value
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* compatible with the INTPIN register (included in the PINTSEL
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* register).
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*/
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intpin = pin;
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if (config->port_num == 1) {
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intpin += 24;
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} else if (config->port_num == 2) {
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intpin += 56;
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}
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if (mode == GPIO_INT_MODE_DISABLED) {
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irq = pintsel_detach(config->shared, intpin);
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} else {
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irq = pintsel_attach(config->shared, intpin);
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}
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if (irq < 0) {
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return irq;
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}
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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pint_regs->isel &= ~BIT(irq);
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pint_regs->cienr |= BIT(irq);
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pint_regs->cienf |= BIT(irq);
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break;
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case GPIO_INT_MODE_EDGE:
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/* Select edge interrupt mode. */
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pint_regs->isel &= ~BIT(irq);
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/* Enable interrupts on falling and/or rising edges. */
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if (trig & GPIO_INT_TRIG_LOW)
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pint_regs->sienf |= BIT(irq);
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else
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pint_regs->cienf |= BIT(irq);
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if (trig & GPIO_INT_TRIG_HIGH)
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pint_regs->sienr |= BIT(irq);
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else
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pint_regs->cienr |= BIT(irq);
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break;
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case GPIO_INT_MODE_LEVEL:
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/* Select level interrupt mode. */
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pint_regs->isel |= BIT(irq);
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/* Set active level. */
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if (trig & GPIO_INT_TRIG_LOW)
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pint_regs->cienf |= BIT(irq);
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else
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pint_regs->sienf |= BIT(irq);
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/* Enable level interrupt. */
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pint_regs->sienr |= BIT(irq);
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break;
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default:
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return -ENOTSUP;
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}
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/* Clear interrupt status. */
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pint_regs->ist |= BIT(irq);
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return 0;
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}
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static int gpio_lpc11u6x_manage_callback(const struct device *port,
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struct gpio_callback *cb, bool set)
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{
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struct gpio_lpc11u6x_data *data = DEV_DATA(port);
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return gpio_manage_callback(&data->cb_list, cb, set);
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}
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static uint32_t gpio_lpc11u6x_get_pending_int(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return -ENOTSUP;
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}
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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DEVICE_DECLARE(gpio_lpc11u6x_0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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DEVICE_DECLARE(gpio_lpc11u6x_1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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DEVICE_DECLARE(gpio_lpc11u6x_2);
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#endif
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static void gpio_lpc11u6x_isr(const void *arg)
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{
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struct gpio_lpc11u6x_shared *shared =
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(struct gpio_lpc11u6x_shared *)arg;
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struct lpc11u6x_pint_regs *pint_regs = (struct lpc11u6x_pint_regs *)
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(shared->gpio_base + LPC11U6X_PINT_REGS);
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uint32_t *pintsel_reg =
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(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);
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uint8_t irq;
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uint32_t pins[3] = { 0, 0, 0 };
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const struct device *port;
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struct gpio_lpc11u6x_data *data;
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for (irq = 0; irq < shared->nirqs; irq++) {
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uint32_t intpin;
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if ((pint_regs->ist & BIT(irq)) == 0) {
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continue;
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}
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/* Clear interrupt status. */
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pint_regs->ist |= BIT(irq);
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/*
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* Look in the PINTSEL register to retrieve the "intpin" value
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* attached with the requested interrupt. Extract the GPIO
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* port and pin numbers from this "intpin" value and store them
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* into an "active pins" mask.
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*/
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intpin = pintsel_reg[irq] & BIT_MASK(5);
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if (intpin < 24) {
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pins[0] |= BIT(intpin);
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} else if (intpin < 56) {
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pins[1] |= BIT(intpin - 24);
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} else {
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pins[2] |= BIT(intpin - 56);
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}
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}
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/* For each port with active pins, fire the GPIO interrupt callbacks. */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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if (pins[0]) {
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port = DEVICE_GET(gpio_lpc11u6x_0);
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data = port->data;
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gpio_fire_callbacks(&data->cb_list, port, pins[0]);
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}
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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if (pins[1]) {
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port = DEVICE_GET(gpio_lpc11u6x_1);
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data = port->data;
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gpio_fire_callbacks(&data->cb_list, port, pins[1]);
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}
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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if (pins[2]) {
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port = DEVICE_GET(gpio_lpc11u6x_2);
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data = port->data;
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gpio_fire_callbacks(&data->cb_list, port, pins[2]);
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}
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#endif
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}
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static const struct gpio_driver_api gpio_lpc11u6x_driver_api = {
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.pin_configure = gpio_lpc11u6x_pin_configure,
|
|
.port_get_raw = gpio_lpc11u6x_port_get_raw,
|
|
.port_set_masked_raw = gpio_lpc11u6x_port_set_masked_raw,
|
|
.port_set_bits_raw = gpio_lpc11u6x_port_set_bits_raw,
|
|
.port_clear_bits_raw = gpio_lpc11u6x_port_clear_bits_raw,
|
|
.port_toggle_bits = gpio_lpc11u6x_port_toggle_bits,
|
|
.pin_interrupt_configure = gpio_lpc11u6x_pin_interrupt_configure,
|
|
.manage_callback = gpio_lpc11u6x_manage_callback,
|
|
.get_pending_int = gpio_lpc11u6x_get_pending_int,
|
|
};
|
|
|
|
/*
|
|
* Note that the first DT instance is used to initialize the resources
|
|
* shared between all the ports (IRQ lines, clock).
|
|
*/
|
|
|
|
static const struct gpio_lpc11u6x_shared gpio_lpc11u6x_shared = {
|
|
.clock_controller_name = DT_LABEL(DT_INST_PHANDLE(0, clocks)),
|
|
.clock_subsys = (clock_control_subsys_t) DT_INST_PHA(0, clocks, clkid),
|
|
.gpio_base = DT_INST_REG_ADDR_BY_IDX(0, 0),
|
|
.syscon_base = DT_INST_REG_ADDR_BY_IDX(0, 1),
|
|
.nirqs = DT_NUM_IRQS(DT_DRV_INST(0)),
|
|
};
|
|
|
|
#define IRQ_INIT(n) \
|
|
do { \
|
|
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, n, irq), \
|
|
DT_INST_IRQ_BY_IDX(0, n, priority), \
|
|
gpio_lpc11u6x_isr, &gpio_lpc11u6x_shared, 0); \
|
|
irq_enable(DT_INST_IRQ_BY_IDX(0, n, irq)); \
|
|
} while (0)
|
|
|
|
static int gpio_lpc11u6x_init(const struct device *dev)
|
|
{
|
|
const struct gpio_lpc11u6x_config *config = DEV_CFG(dev);
|
|
struct gpio_lpc11u6x_data *data = DEV_DATA(dev);
|
|
const struct device *clock_dev;
|
|
int ret;
|
|
static bool gpio_ready;
|
|
|
|
/* Retrieve pinmux device. */
|
|
data->pinmux_dev = device_get_binding(config->pinmux_name);
|
|
if (!data->pinmux_dev) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Initialize shared resources only once. */
|
|
if (gpio_ready) {
|
|
return 0;
|
|
}
|
|
|
|
/* Enable GPIO and PINT clocks. */
|
|
clock_dev = device_get_binding(config->shared->clock_controller_name);
|
|
if (!clock_dev) {
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = clock_control_on(clock_dev, config->shared->clock_subsys);
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
|
|
#if DT_INST_IRQ_HAS_IDX(0, 0)
|
|
IRQ_INIT(0);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 1)
|
|
IRQ_INIT(1);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 2)
|
|
IRQ_INIT(2);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 3)
|
|
IRQ_INIT(3);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 4)
|
|
IRQ_INIT(4);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 5)
|
|
IRQ_INIT(5);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 6)
|
|
IRQ_INIT(6);
|
|
#endif
|
|
#if DT_INST_IRQ_HAS_IDX(0, 7)
|
|
IRQ_INIT(7);
|
|
#endif
|
|
gpio_ready = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define GPIO_LPC11U6X_INIT(id) \
|
|
static const struct gpio_lpc11u6x_config \
|
|
gpio_lpc11u6x_config_##id = { \
|
|
.common = { \
|
|
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE( \
|
|
DT_NODELABEL(gpio##id)), \
|
|
}, \
|
|
.shared = &gpio_lpc11u6x_shared, \
|
|
.port_num = id, \
|
|
.pinmux_name = DT_LABEL(DT_PHANDLE(DT_NODELABEL(gpio##id), \
|
|
pinmux_port)), \
|
|
.ngpios = DT_PROP(DT_NODELABEL(gpio##id), ngpios), \
|
|
}; \
|
|
\
|
|
static struct gpio_lpc11u6x_data gpio_lpc11u6x_data_##id; \
|
|
\
|
|
DEVICE_AND_API_INIT(gpio_lpc11u6x_##id, \
|
|
DT_LABEL(DT_NODELABEL(gpio##id)), \
|
|
&gpio_lpc11u6x_init, \
|
|
&gpio_lpc11u6x_data_##id, \
|
|
&gpio_lpc11u6x_config_##id, \
|
|
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&gpio_lpc11u6x_driver_api)
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
|
|
GPIO_LPC11U6X_INIT(0);
|
|
#endif
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
|
|
GPIO_LPC11U6X_INIT(1);
|
|
#endif
|
|
|
|
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
|
|
GPIO_LPC11U6X_INIT(2);
|
|
#endif
|