36 lines
821 B
C
36 lines
821 B
C
/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <arch/arm/cortex_m/mpu/arm_mpu.h>
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#include "arm_mpu_mem_cfg.h"
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/* SoC Private Peripheral Bus */
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#define PPB_BASE 0xE0000000
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static const struct arm_mpu_region mpu_regions[] = {
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/* Region 0 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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/* Region 1 */
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MPU_REGION_ENTRY("RAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
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/* Region 2 */
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#ifdef REGION_SRAM_1_SIZE
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MPU_REGION_ENTRY("RAM_1",
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(CONFIG_SRAM_BASE_ADDRESS + REGION_SRAM_1_START),
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REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
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#endif
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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