50d72ed9c9
Speculative execution side channel attacks can read the entire FPU/SIMD register state on affected Intel Core processors, see CVE-2018-3665. We now have two options for managing floating point context between threads on x86: CONFIG_EAGER_FP_SHARING and CONFIG_LAZY_FP_SHARING. The mitigation is to unconditionally save/restore these registers on context switch, instead of the lazy sharing algorithm used by CONFIG_LAZY_FP_SHARING. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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| offsets.c | ||