602 lines
15 KiB
C
602 lines
15 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARC Timer0 device driver
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*
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* This module implements a kernel device driver for the ARCv2 processor Timer0
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* and provides the standard "system clock driver" interfaces.
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*
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* If the TICKLESS_IDLE kernel configuration option is enabled, the timer may
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* be programmed to wake the system in N >= TICKLESS_IDLE_THRESH ticks. The
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* kernel invokes _timer_idle_enter() to program the up counter to trigger an
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* interrupt in N ticks. When the timer expires (or when another interrupt is
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* detected), the kernel's interrupt stub invokes _timer_idle_exit() to leave
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* the tickless idle state.
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*
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* @internal
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* The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero
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* counter.
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*
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* Factors that increase the driver's tickless idle complexity:
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* 1. As the Timer0 up-counter is a 32-bit value, the number of ticks for which
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* the system can be in tickless idle is limited to 'max_system_ticks'.
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*
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* 2. The act of entering tickless idle may potentially straddle a tick
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* boundary. This can be detected in _timer_idle_enter() after Timer0 is
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* programmed with the new limit and acted upon in _timer_idle_exit().
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*
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* 3. Tickless idle may be prematurely aborted due to a straddled tick. See
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* previous factor.
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*
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* 4. Tickless idle may end naturally. This is detected and handled in
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* _timer_idle_exit().
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*
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* 5. Tickless idle may be prematurely aborted due to a non-timer interrupt.
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* If this occurs, Timer0 is reprogrammed to trigger at the next tick.
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* @endinternal
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <misc/__assert.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <sys_clock.h>
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#include <drivers/system_timer.h>
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#include <stdbool.h>
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#include <misc/__assert.h>
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/*
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* note: This implementation assumes Timer0 is present. Be sure
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* to build the ARC CPU with Timer0.
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*/
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#include <board.h>
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#define _ARC_V2_TMR_CTRL_IE 0x1 /* interrupt enable */
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#define _ARC_V2_TMR_CTRL_NH 0x2 /* count only while not halted */
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#define _ARC_V2_TMR_CTRL_W 0x4 /* watchdog mode enable */
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#define _ARC_V2_TMR_CTRL_IP 0x8 /* interrupt pending flag */
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/* running total of timer count */
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static u32_t __noinit cycles_per_tick;
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static volatile u32_t accumulated_cycle_count;
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#ifdef CONFIG_TICKLESS_IDLE
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static u32_t __noinit max_system_ticks;
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static u32_t __noinit programmed_ticks;
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extern s32_t _sys_idle_elapsed_ticks;
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#ifndef CONFIG_TICKLESS_KERNEL
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static u32_t __noinit programmed_limit;
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static int straddled_tick_on_idle_enter;
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#endif
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#endif
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#ifdef CONFIG_TICKLESS_KERNEL
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static volatile int timer_expired;
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#endif
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static u32_t arcv2_timer0_device_power_state;
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static u32_t saved_limit;
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static u32_t saved_control;
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#endif
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/**
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*
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* @brief Get contents of Timer0 count register
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*
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* @return Current Timer0 count
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*/
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static ALWAYS_INLINE u32_t timer0_count_register_get(void)
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{
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return _arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
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}
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/**
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*
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* @brief Set Timer0 count register to the specified value
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void timer0_count_register_set(u32_t value)
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{
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, value);
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}
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/**
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*
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* @brief Get contents of Timer0 control register
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*
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* @return N/A
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*/
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static ALWAYS_INLINE u32_t timer0_control_register_get(void)
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{
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return _arc_v2_aux_reg_read(_ARC_V2_TMR0_CONTROL);
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}
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/**
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*
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* @brief Set Timer0 control register to the specified value
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void timer0_control_register_set(u32_t value)
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{
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_CONTROL, value);
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}
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/**
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*
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* @brief Get contents of Timer0 limit register
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*
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* @return N/A
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*/
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static ALWAYS_INLINE u32_t timer0_limit_register_get(void)
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{
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return _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
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}
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/**
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*
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* @brief Set Timer0 limit register to the specified value
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void timer0_limit_register_set(u32_t count)
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{
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_LIMIT, count);
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}
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#ifdef CONFIG_TICKLESS_IDLE
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static ALWAYS_INLINE void update_accumulated_count(void)
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{
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accumulated_cycle_count += (_sys_idle_elapsed_ticks * cycles_per_tick);
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}
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#else /* CONFIG_TICKLESS_IDLE */
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static ALWAYS_INLINE void update_accumulated_count(void)
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{
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accumulated_cycle_count += cycles_per_tick;
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}
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#endif /* CONFIG_TICKLESS_IDLE */
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#ifdef CONFIG_TICKLESS_KERNEL
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static inline void program_max_cycles(void)
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{
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timer0_limit_register_set(max_system_ticks * cycles_per_tick);
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timer_expired = 0;
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}
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#endif
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/**
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*
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* @brief System clock periodic tick handler
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*
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* This routine handles the system clock periodic tick interrupt. It always
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* announces one tick.
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*
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* @return N/A
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*/
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void _timer_int_handler(void *unused)
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{
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ARG_UNUSED(unused);
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/* clear the interrupt by writing 0 to IP bit of the control register */
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timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
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#ifdef CONFIG_TICKLESS_KERNEL
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if (!programmed_ticks) {
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if (_sys_clock_always_on) {
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_sys_clock_tick_count = _get_elapsed_clock_time();
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program_max_cycles();
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}
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return;
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}
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_sys_idle_elapsed_ticks = programmed_ticks;
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/*
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* Clear programmed ticks before announcing elapsed time so
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* that recursive calls to _update_elapsed_time() will not
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* announce already consumed elapsed time
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*/
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programmed_ticks = 0;
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timer_expired = 1;
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_sys_clock_tick_announce();
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/* _sys_clock_tick_announce() could cause new programming */
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if (!programmed_ticks && _sys_clock_always_on) {
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_sys_clock_tick_count = _get_elapsed_clock_time();
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program_max_cycles();
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}
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#else
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#if defined(CONFIG_TICKLESS_IDLE)
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timer0_limit_register_set(cycles_per_tick - 1);
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__ASSERT_EVAL({},
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u32_t timer_count = timer0_count_register_get(),
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timer_count <= (cycles_per_tick - 1),
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"timer_count: %d, limit %d\n", timer_count, cycles_per_tick - 1);
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_sys_clock_final_tick_announce();
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#else
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_sys_clock_tick_announce();
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#endif
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update_accumulated_count();
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#endif
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}
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#ifdef CONFIG_TICKLESS_KERNEL
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u32_t _get_program_time(void)
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{
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return programmed_ticks;
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}
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u32_t _get_remaining_program_time(void)
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{
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if (programmed_ticks == 0) {
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return 0;
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}
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if (timer0_control_register_get() & _ARC_V2_TMR_CTRL_IP) {
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return 0;
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}
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return programmed_ticks -
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(timer0_count_register_get() / cycles_per_tick);
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}
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u32_t _get_elapsed_program_time(void)
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{
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if (programmed_ticks == 0) {
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return 0;
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}
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if (timer0_control_register_get() & _ARC_V2_TMR_CTRL_IP) {
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return programmed_ticks;
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}
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return timer0_count_register_get() / cycles_per_tick;
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}
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void _set_time(u32_t time)
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{
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if (!time) {
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programmed_ticks = 0;
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return;
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}
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programmed_ticks = time > max_system_ticks ? max_system_ticks : time;
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_sys_clock_tick_count = _get_elapsed_clock_time();
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timer0_limit_register_set(programmed_ticks * cycles_per_tick);
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timer0_count_register_set(0);
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timer_expired = 0;
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}
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void _enable_sys_clock(void)
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{
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if (!programmed_ticks) {
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program_max_cycles();
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}
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}
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static inline u64_t get_elapsed_count(void)
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{
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u64_t elapsed;
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if (timer_expired
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|| (timer0_control_register_get() & _ARC_V2_TMR_CTRL_IP)) {
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elapsed = timer0_limit_register_get();
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} else {
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elapsed = timer0_count_register_get();
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}
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elapsed += _sys_clock_tick_count * cycles_per_tick;
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return elapsed;
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}
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u64_t _get_elapsed_clock_time(void)
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{
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return get_elapsed_count() / cycles_per_tick;
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}
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#endif
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#if defined(CONFIG_TICKLESS_IDLE)
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/*
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* @brief initialize the tickless idle feature
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*
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* This routine initializes the tickless idle feature.
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*
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* @return N/A
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*/
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static void tickless_idle_init(void)
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{
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/* calculate the max number of ticks with this 32-bit H/W counter */
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max_system_ticks = 0xffffffff / cycles_per_tick;
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}
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/*
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* @brief Place the system timer into idle state
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*
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* Re-program the timer to enter into the idle state for either the given
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* number of ticks or the maximum number of ticks that can be programmed
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* into hardware.
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*
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* @return N/A
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*/
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void _timer_idle_enter(s32_t ticks)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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if (ticks != K_FOREVER) {
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/* Need to reprogram only if current program is smaller */
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if (ticks > programmed_ticks) {
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_set_time(ticks);
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}
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} else {
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programmed_ticks = 0;
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timer0_control_register_set(timer0_control_register_get() &
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~_ARC_V2_TMR_CTRL_IE);
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}
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#else
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u32_t status;
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if ((ticks == K_FOREVER) || (ticks > max_system_ticks)) {
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/*
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* The number of cycles until the timer must fire next might not fit
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* in the 32-bit counter register. To work around this, program
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* the counter to fire in the maximum number of ticks.
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*/
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ticks = max_system_ticks;
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}
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programmed_ticks = ticks;
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programmed_limit = (programmed_ticks * cycles_per_tick) - 1;
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timer0_limit_register_set(programmed_limit);
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/*
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* If Timer0's IP bit is set, then it is known that we have straddled
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* a tick boundary while entering tickless idle.
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*/
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status = timer0_control_register_get();
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if (status & _ARC_V2_TMR_CTRL_IP) {
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straddled_tick_on_idle_enter = 1;
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}
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__ASSERT_EVAL({},
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u32_t timer_count = timer0_count_register_get(),
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timer_count <= programmed_limit,
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"timer_count: %d, limit %d\n", timer_count, programmed_limit);
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#endif
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}
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/*
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* @brief handling of tickless idle when interrupted
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*
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* The routine, called by _SysPowerSaveIdleExit, is responsible for taking the
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* timer out of idle mode and generating an interrupt at the next tick
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* interval. It is expected that interrupts have been disabled.
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*
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* RETURNS: N/A
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*/
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void _timer_idle_exit(void)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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if (!programmed_ticks && _sys_clock_always_on) {
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if (!(timer0_control_register_get() & _ARC_V2_TMR_CTRL_IE)) {
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timer0_control_register_set(_ARC_V2_TMR_CTRL_NH |
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_ARC_V2_TMR_CTRL_IE);
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}
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program_max_cycles();
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}
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#else
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if (straddled_tick_on_idle_enter) {
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/* Aborting the tickless idle due to a straddled tick. */
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straddled_tick_on_idle_enter = 0;
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__ASSERT_EVAL({},
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u32_t timer_count = timer0_count_register_get(),
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timer_count <= programmed_limit,
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"timer_count: %d, limit %d\n", timer_count, programmed_limit);
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return;
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}
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u32_t control;
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u32_t current_count;
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current_count = timer0_count_register_get();
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control = timer0_control_register_get();
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if (control & _ARC_V2_TMR_CTRL_IP) {
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/*
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* The timer has expired. The handler _timer_int_handler() is
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* guaranteed to execute. Track the number of elapsed ticks. The
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* handler _timer_int_handler() will account for the final tick.
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*/
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_sys_idle_elapsed_ticks = programmed_ticks - 1;
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update_accumulated_count();
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_sys_clock_tick_announce();
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__ASSERT_EVAL({},
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u32_t timer_count = timer0_count_register_get(),
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timer_count <= programmed_limit,
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"timer_count: %d, limit %d\n", timer_count, programmed_limit);
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return;
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}
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/*
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* A non-timer interrupt occurred. Announce any
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* ticks that have elapsed during the tickless idle.
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*/
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_sys_idle_elapsed_ticks = current_count / cycles_per_tick;
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if (_sys_idle_elapsed_ticks > 0) {
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update_accumulated_count();
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_sys_clock_tick_announce();
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}
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/*
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* Ensure the timer will expire at the end of the next tick in case
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* the ISR makes any threads ready to run.
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*/
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timer0_limit_register_set(cycles_per_tick - 1);
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timer0_count_register_set(current_count % cycles_per_tick);
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__ASSERT_EVAL({},
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u32_t timer_count = timer0_count_register_get(),
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timer_count <= (cycles_per_tick - 1),
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"timer_count: %d, limit %d\n", timer_count, cycles_per_tick-1);
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#endif
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}
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#else
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static void tickless_idle_init(void) {}
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#endif /* CONFIG_TICKLESS_IDLE */
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/**
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*
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* @brief Initialize and enable the system clock
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*
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* This routine is used to program the ARCv2 timer to deliver interrupts at the
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* rate specified via the 'sys_clock_us_per_tick' global variable.
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*
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* @return 0
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*/
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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/* ensure that the timer will not generate interrupts */
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timer0_control_register_set(0);
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timer0_count_register_set(0);
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cycles_per_tick = sys_clock_hw_cycles_per_tick;
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IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY,
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_timer_int_handler, NULL, 0);
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/*
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* Set the reload value to achieve the configured tick rate, enable the
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* counter and interrupt generation.
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*/
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tickless_idle_init();
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timer0_limit_register_set(cycles_per_tick - 1);
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timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
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/* everything has been configured: safe to enable the interrupt */
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irq_enable(IRQ_TIMER0);
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return 0;
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}
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static int sys_clock_suspend(struct device *dev)
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{
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ARG_UNUSED(dev);
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saved_limit = timer0_limit_register_get();
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saved_control = timer0_control_register_get();
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arcv2_timer0_device_power_state = DEVICE_PM_SUSPEND_STATE;
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return 0;
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}
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static int sys_clock_resume(struct device *dev)
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{
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ARG_UNUSED(dev);
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timer0_limit_register_set(saved_limit);
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timer0_control_register_set(saved_control);
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/*
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* It is difficult to accurately know the time spent in DS.
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* Expire the timer to get the scheduler called.
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*/
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timer0_count_register_set(saved_limit - 1);
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arcv2_timer0_device_power_state = DEVICE_PM_ACTIVE_STATE;
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return 0;
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}
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/*
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|
* Implements the driver control management functionality
|
|
* the *context may include IN data or/and OUT data
|
|
*/
|
|
int sys_clock_device_ctrl(struct device *port, u32_t ctrl_command,
|
|
void *context)
|
|
{
|
|
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
|
|
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
|
|
return sys_clock_suspend(port);
|
|
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
|
|
return sys_clock_resume(port);
|
|
}
|
|
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
|
|
*((u32_t *)context) = arcv2_timer0_device_power_state;
|
|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
|
|
|
|
u32_t _timer_cycle_get_32(void)
|
|
{
|
|
#ifdef CONFIG_TICKLESS_KERNEL
|
|
return (u32_t) get_elapsed_count();
|
|
#else
|
|
u32_t acc, count;
|
|
|
|
do {
|
|
acc = accumulated_cycle_count;
|
|
count = timer0_count_register_get();
|
|
} while (acc != accumulated_cycle_count);
|
|
|
|
return acc + count;
|
|
#endif
|
|
}
|
|
|
|
#if defined(CONFIG_SYSTEM_CLOCK_DISABLE)
|
|
/**
|
|
*
|
|
* @brief Stop announcing ticks into the kernel
|
|
*
|
|
* This routine disables timer interrupt generation and delivery.
|
|
* Note that the timer's counting cannot be stopped by software.
|
|
*
|
|
* @return N/A
|
|
*/
|
|
void sys_clock_disable(void)
|
|
{
|
|
unsigned int key; /* interrupt lock level */
|
|
u32_t control; /* timer control register value */
|
|
|
|
key = irq_lock();
|
|
|
|
/* disable interrupt generation */
|
|
|
|
control = timer0_control_register_get();
|
|
timer0_control_register_set(control & ~_ARC_V2_TMR_CTRL_IE);
|
|
|
|
irq_unlock(key);
|
|
|
|
/* disable interrupt in the interrupt controller */
|
|
|
|
irq_disable(ARCV2_TIMER0_INT_LVL);
|
|
}
|
|
#endif /* CONFIG_SYSTEM_CLOCK_DISABLE */
|