27 lines
567 B
Plaintext
27 lines
567 B
Plaintext
# Microchip MEC172x MCU core series
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# Copyright (c) 2021 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "MEC172x Selection"
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depends on SOC_SERIES_MEC172X
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config SOC_MEC172X_NSZ
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bool "MEC172X_NSZ"
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endchoice
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config RTOS_TIMER
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bool "MEC172x RTOS Timer(32KHz) as kernel timer"
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config SOC_MEC172X_PROC_CLK_DIV
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int "PROC_CLK_DIV"
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default 1
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range 1 48
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help
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This divisor defines a ratio between processor clock (HCLK)
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and main 96 MHz clock (MCK):
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HCLK = MCK / PROC_CLK_DIV
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Allowed divider values: 1, 3, 4, 16, and 48.
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