203 lines
6.2 KiB
C
203 lines
6.2 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_
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#include <dt-bindings/pcie/pcie.h>
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @typedef pcie_bdf_t
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* @brief A unique PCI(e) endpoint (bus, device, function).
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*
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* A PCI(e) endpoint is uniquely identified topologically using a
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* (bus, device, function) tuple. The internal structure is documented
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* in include/dt-bindings/pcie/pcie.h: see PCIE_BDF() and friends, since
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* these tuples are referenced from devicetree.
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*/
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typedef u32_t pcie_bdf_t;
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/**
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* @typedef pcie_id_t
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* @brief A unique PCI(e) identifier (vendor ID, device ID).
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*
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* The PCIE_CONF_ID register for each endpoint is a (vendor ID, device ID)
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* pair, which is meant to tell the system what the PCI(e) endpoint is. Again,
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* look to PCIE_ID_* macros in include/dt-bindings/pcie/pcie.h for more.
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*/
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typedef u32_t pcie_id_t;
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/*
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* These functions are arch-, board-, or SoC-specific.
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*/
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/**
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* @brief Read a 32-bit word from an endpoint's configuration space.
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*
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* This function is exported by the arch/SoC/board code.
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*
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @return the word read (0xFFFFFFFFU if nonexistent endpoint or word)
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*/
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extern u32_t pcie_conf_read(pcie_bdf_t bdf, unsigned int reg);
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/**
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* @brief Write a 32-bit word to an endpoint's configuration space.
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*
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* This function is exported by the arch/SoC/board code.
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*
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* @param bdf PCI(e) endpoint
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* @param reg the configuration word index (not address)
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* @param data the value to write
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*/
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extern void pcie_conf_write(pcie_bdf_t bdf, unsigned int reg, u32_t data);
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/**
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* @brief Probe for the presence of a PCI(e) endpoint.
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*
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* @param bdf the endpoint to probe
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* @param id the endpoint ID to expect, or PCI_ID_ANY for "any device"
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* @return true if the device is present, false otherwise
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*/
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extern bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id);
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/**
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* @brief Get the nth MMIO address assigned to an endpoint.
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* @param bdf the PCI(e) endpoint
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* @param index (0-based) index
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* @return the (32-bit) address, or PCI_CONF_BAR_NONE if nonexistent.
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*
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* A PCI(e) endpoint has 0 or more memory-mapped regions. This function
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* allows the caller to enumerate them by calling with index=0..n. If
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* PCI_CONF_BAR_NONE is returned, there are no further regions. The indices
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* are order-preserving with respect to the endpoint BARs: e.g., index 0
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* will return the lowest-numbered memory BAR on the endpoint.
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*/
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extern u32_t pcie_get_mbar(pcie_bdf_t bdf, unsigned int index);
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/**
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* @brief Get the nth I/O address assigned to an endpoint.
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* @param bdf the PCI(e) endpoint
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* @param index (0-based) index
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* @return the (32-bit) address, or PCI_CONF_BAR_NONE if nonexistent.
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*
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* Analogous to pcie_get_mbar(), except returns I/O region data.
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*/
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extern u32_t pcie_get_iobar(pcie_bdf_t bdf, unsigned int index);
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/**
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* @brief Set or reset bits in the endpoint command/status register.
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*
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* @param bdf the PCI(e) endpoint
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* @param bits the powerset of bits of interest
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* @param on use true to set bits, false to reset them
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*/
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extern void pcie_set_cmd(pcie_bdf_t bdf, u32_t bits, bool on);
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/**
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* @brief Return the IRQ assigned by the firmware/board to an endpoint.
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*
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* @param bdf the PCI(e) endpoint
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* @return the IRQ number, or PCIE_CONF_INTR_IRQ_NONE if unknown.
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*/
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extern unsigned int pcie_wired_irq(pcie_bdf_t bdf);
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/**
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* @brief Enable the PCI(e) endpoint to generate the specified IRQ.
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*
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* @param bdf the PCI(e) endpoint
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* @param irq the IRQ to generate
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*
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* If MSI is enabled and the endpoint supports it, the endpoint will
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* be configured to generate the specified IRQ via MSI. Otherwise, it
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* is assumed that the IRQ IRQ has been routed by the boot firmware
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* to the specified IRQ, and the IRQ is enabled (at the I/O APIC, or
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* wherever appropriate).
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*/
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extern void pcie_irq_enable(pcie_bdf_t bdf, unsigned int irq);
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/*
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* Configuration word 0 aligns directly with pcie_id_t.
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*/
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#define PCIE_CONF_ID 0U
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/*
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* Configuration word 1 contains command and status bits.
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*/
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#define PCIE_CONF_CMDSTAT 1U /* command/status register */
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#define PCIE_CONF_CMDSTAT_IO 0x00000001U /* I/O access enable */
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#define PCIE_CONF_CMDSTAT_MEM 0x00000002U /* mem access enable */
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#define PCIE_CONF_CMDSTAT_MASTER 0x00000004U /* bus master enable */
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#define PCIE_CONF_CMDSTAT_CAPS 0x00100000U /* capabilities list */
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/*
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* Configuration word 2 has additional function identification that
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* we only care about for debug output (PCIe shell commands).
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*/
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#define PCIE_CONF_CLASSREV 2U /* class/revision register */
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#define PCIE_CONF_CLASSREV_CLASS(w) (((w) >> 24) & 0xFFU)
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#define PCIE_CONF_CLASSREV_SUBCLASS(w) (((w) >> 16) & 0xFFU)
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#define PCIE_CONF_CLASSREV_PROGIF(w) (((w) >> 8) & 0xFFU)
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#define PCIE_CONF_CLASSREV_REV(w) ((w) & 0xFFU)
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/*
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* The only part of configuration word 3 that is of interest to us is
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* the header type, as we use it to distinguish functional endpoints
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* from bridges (which are, for our purposes, transparent).
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*/
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#define PCIE_CONF_TYPE 3U
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#define PCIE_CONF_TYPE_BRIDGE(w) (((w) & 0x007F0000U) != 0U)
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/*
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* Words 4-9 are BARs are I/O or memory decoders. Memory decoders may
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* be 64-bit decoders, in which case the next configuration word holds
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* the high-order bits (and is, thus, not a BAR itself).
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*/
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#define PCIE_CONF_BAR0 4U
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#define PCIE_CONF_BAR1 5U
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#define PCIE_CONF_BAR2 6U
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#define PCIE_CONF_BAR3 7U
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#define PCIE_CONF_BAR4 8U
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#define PCIE_CONF_BAR5 9U
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#define PCIE_CONF_BAR_IO(w) (((w) & 0x00000001U) == 0x00000001U)
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#define PCIE_CONF_BAR_MEM(w) (((w) & 0x00000001U) != 0x00000001U)
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#define PCIE_CONF_BAR_64(w) (((w) & 0x00000006U) == 0x00000004U)
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#define PCIE_CONF_BAR_ADDR(w) ((w) & 0xFFFFFFF0U)
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#define PCIE_CONF_BAR_NONE 0U
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/*
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* Word 15 contains information related to interrupts.
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*
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* We're only interested in the low byte, which is [supposed to be] set by
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* the firmware to indicate which wire IRQ the device interrupt is routed to.
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*/
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#define PCIE_CONF_INTR 15U
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#define PCIE_CONF_INTR_IRQ(w) ((w) & 0xFFU)
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#define PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PCIE_PCIE_H_ */
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