554 lines
13 KiB
C
554 lines
13 KiB
C
/*
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* Copyright (c) 2024 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc_v5.h"
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/riscv/csr.h>
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#include <zephyr/drivers/cache.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(cache_andes, CONFIG_CACHE_LOG_LEVEL);
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/* L1 CCTL Command */
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#define CCTL_L1D_VA_INVAL 0
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#define CCTL_L1D_VA_WB 1
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#define CCTL_L1D_VA_WBINVAL 2
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#define CCTL_L1D_WBINVAL_ALL 6
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#define CCTL_L1D_WB_ALL 7
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#define CCTL_L1I_VA_INVAL 8
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#define CCTL_L1D_INVAL_ALL 23
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#define CCTL_L1I_IX_INVAL 24
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/* mcache_ctl bitfield */
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#define MCACHE_CTL_IC_EN BIT(0)
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#define MCACHE_CTL_DC_EN BIT(1)
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#define MCACHE_CTL_CCTL_SUEN BIT(8)
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#define MCACHE_CTL_DC_COHEN BIT(19)
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#define MCACHE_CTL_DC_COHSTA BIT(20)
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/* micm_cfg bitfield */
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#define MICM_CFG_ISET BIT_MASK(3)
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#define MICM_CFG_IWAY_SHIFT 3
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#define MICM_CFG_ISZ_SHIFT 6
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/* mdcm_cfg bitfield */
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#define MDCM_CFG_DSZ_SHIFT 6
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/* mmsc_cfg bitfield */
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#define MMSC_CFG_CCTLCSR BIT(16)
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#define MMSC_CFG_VCCTL_2 BIT(19)
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#define MMSC_CFG_MSC_EXT BIT(31)
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#define MMSC_CFG_RVARCH BIT64(52)
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/* mmsc_cfg2 bitfield */
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#define MMSC_CFG2_RVARCH BIT(20)
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/* mrvarch_cfg bitfield */
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#define MRVARCH_CFG_SMEPMP BIT(4)
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#define K_CACHE_WB BIT(0)
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#define K_CACHE_INVD BIT(1)
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#define K_CACHE_WB_INVD (K_CACHE_WB | K_CACHE_INVD)
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struct cache_config {
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uint32_t instr_line_size;
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uint32_t data_line_size;
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uint32_t l2_cache_size;
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uint32_t l2_cache_inclusive;
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};
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static struct cache_config cache_cfg;
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static struct k_spinlock lock;
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#if DT_NODE_HAS_COMPAT_STATUS(DT_INST(0, andestech_l2c), andestech_l2c, okay)
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#include "cache_andes_l2.h"
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#else
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static ALWAYS_INLINE void nds_l2_cache_enable(void) { }
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static ALWAYS_INLINE void nds_l2_cache_disable(void) { }
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static ALWAYS_INLINE int nds_l2_cache_range(void *addr, size_t size, int op) { return 0; }
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static ALWAYS_INLINE int nds_l2_cache_all(int op) { return 0; }
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static ALWAYS_INLINE int nds_l2_cache_is_inclusive(void) { return 0; }
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static ALWAYS_INLINE int nds_l2_cache_init(void) { return 0; }
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#endif /* DT_NODE_HAS_COMPAT_STATUS(DT_INST(0, andestech_l2c), andestech_l2c, okay) */
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static ALWAYS_INLINE int nds_cctl_range_operations(void *addr, size_t size, int line_size, int cmd)
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{
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unsigned long last_byte, align_addr;
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unsigned long status = csr_read(mstatus);
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last_byte = (unsigned long)addr + size - 1;
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align_addr = ROUND_DOWN(addr, line_size);
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/*
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* In memory access privilige U mode, applications should use ucctl CSRs
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* for VA type commands.
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*/
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if ((status & MSTATUS_MPRV) && !(status & MSTATUS_MPP)) {
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while (align_addr <= last_byte) {
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csr_write(NDS_UCCTLBEGINADDR, align_addr);
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csr_write(NDS_UCCTLCOMMAND, cmd);
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align_addr += line_size;
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}
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} else {
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while (align_addr <= last_byte) {
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csr_write(NDS_MCCTLBEGINADDR, align_addr);
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csr_write(NDS_MCCTLCOMMAND, cmd);
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align_addr += line_size;
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}
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}
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return 0;
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}
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static ALWAYS_INLINE int nds_l1i_cache_all(int op)
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{
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unsigned long sets, ways, end;
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unsigned long status = csr_read(mstatus);
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if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {
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/*
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* In memory access privilige U mode, applications can only use
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* VA type commands for specific range.
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*/
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if ((status & MSTATUS_MPRV) && !(status & MSTATUS_MPP)) {
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return -ENOTSUP;
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}
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}
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if (op == K_CACHE_INVD) {
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sets = 0x40 << (csr_read(NDS_MICM_CFG) & MICM_CFG_ISET);
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ways = ((csr_read(NDS_MICM_CFG) >> MICM_CFG_IWAY_SHIFT) & BIT_MASK(3)) + 1;
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end = ways * sets * cache_cfg.instr_line_size;
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for (int i = 0; i < end; i += cache_cfg.instr_line_size) {
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csr_write(NDS_MCCTLBEGINADDR, i);
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csr_write(NDS_MCCTLCOMMAND, CCTL_L1I_IX_INVAL);
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}
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}
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return 0;
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}
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static ALWAYS_INLINE int nds_l1d_cache_all(int op)
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{
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unsigned long status = csr_read(mstatus);
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if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {
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/*
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* In memory access privilige U mode, applications can only use
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* VA type commands for specific range.
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*/
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if ((status & MSTATUS_MPRV) && !(status & MSTATUS_MPP)) {
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return -ENOTSUP;
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}
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}
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switch (op) {
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case K_CACHE_WB:
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csr_write(NDS_MCCTLCOMMAND, CCTL_L1D_WB_ALL);
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break;
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case K_CACHE_INVD:
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csr_write(NDS_MCCTLCOMMAND, CCTL_L1D_INVAL_ALL);
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break;
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case K_CACHE_WB_INVD:
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csr_write(NDS_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static ALWAYS_INLINE int nds_l1i_cache_range(void *addr, size_t size, int op)
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{
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unsigned long cmd;
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if (op == K_CACHE_INVD) {
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cmd = CCTL_L1I_VA_INVAL;
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nds_cctl_range_operations(addr, size, cache_cfg.instr_line_size, cmd);
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}
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return 0;
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}
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static ALWAYS_INLINE int nds_l1d_cache_range(void *addr, size_t size, int op)
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{
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unsigned long cmd;
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switch (op) {
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case K_CACHE_WB:
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cmd = CCTL_L1D_VA_WB;
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break;
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case K_CACHE_INVD:
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cmd = CCTL_L1D_VA_INVAL;
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break;
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case K_CACHE_WB_INVD:
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cmd = CCTL_L1D_VA_WBINVAL;
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break;
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default:
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return -ENOTSUP;
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}
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nds_cctl_range_operations(addr, size, cache_cfg.data_line_size, cmd);
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return 0;
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}
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void cache_data_enable(void)
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{
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if (IS_ENABLED(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)) {
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return;
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}
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K_SPINLOCK(&lock) {
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nds_l2_cache_enable();
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/* Enable D-cache coherence management */
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csr_set(NDS_MCACHE_CTL, MCACHE_CTL_DC_COHEN);
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/* Check if CPU support CM or not. */
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if (csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
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/* Wait for cache coherence enabling completed */
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while (!(csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)) {
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;
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}
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}
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/* Enable D-cache */
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csr_set(NDS_MCACHE_CTL, MCACHE_CTL_DC_EN);
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}
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}
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void cache_data_disable(void)
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{
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unsigned long status = csr_read(mstatus);
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if (IS_ENABLED(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)) {
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return;
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}
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if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {
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if ((status & MSTATUS_MPRV) && !(status & MSTATUS_MPP)) {
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if (!cache_cfg.l2_cache_inclusive) {
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return;
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}
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}
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}
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_inclusive) {
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nds_l2_cache_all(K_CACHE_WB_INVD);
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} else {
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nds_l1d_cache_all(K_CACHE_WB_INVD);
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nds_l2_cache_all(K_CACHE_WB_INVD);
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}
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csr_clear(NDS_MCACHE_CTL, MCACHE_CTL_DC_EN);
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/* Check if CPU support CM or not. */
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if (csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA) {
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csr_clear(NDS_MCACHE_CTL, MCACHE_CTL_DC_COHEN);
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/* Wait for cache coherence disabling completed */
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while (csr_read(NDS_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA) {
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;
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}
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}
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nds_l2_cache_disable();
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}
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}
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void cache_instr_enable(void)
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{
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if (IS_ENABLED(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)) {
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return;
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}
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csr_set(NDS_MCACHE_CTL, MCACHE_CTL_IC_EN);
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}
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void cache_instr_disable(void)
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{
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if (IS_ENABLED(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)) {
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return;
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}
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csr_clear(NDS_MCACHE_CTL, MCACHE_CTL_IC_EN);
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}
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int cache_data_invd_all(void)
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{
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unsigned long ret = 0;
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_inclusive) {
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ret |= nds_l2_cache_all(K_CACHE_WB);
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ret |= nds_l2_cache_all(K_CACHE_INVD);
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} else {
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ret |= nds_l1d_cache_all(K_CACHE_WB);
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ret |= nds_l2_cache_all(K_CACHE_WB);
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ret |= nds_l2_cache_all(K_CACHE_INVD);
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ret |= nds_l1d_cache_all(K_CACHE_INVD);
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}
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}
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return ret;
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}
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int cache_data_invd_range(void *addr, size_t size)
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{
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unsigned long ret = 0;
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_inclusive) {
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ret |= nds_l2_cache_range(addr, size, K_CACHE_INVD);
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} else {
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ret |= nds_l2_cache_range(addr, size, K_CACHE_INVD);
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ret |= nds_l1d_cache_range(addr, size, K_CACHE_INVD);
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}
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}
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return ret;
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}
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int cache_instr_invd_all(void)
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{
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unsigned long ret = 0;
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if (IS_ENABLED(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)) {
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return -ENOTSUP;
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}
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if (IS_ENABLED(CONFIG_RISCV_PMP)) {
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/* CCTL IX type command is not to RISC-V Smepmp */
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if (IS_ENABLED(CONFIG_64BIT)) {
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if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_RVARCH) {
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if (csr_read(NDS_MRVARCH_CFG) & MRVARCH_CFG_SMEPMP) {
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return -ENOTSUP;
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}
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}
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} else {
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if ((csr_read(NDS_MMSC_CFG) & MMSC_CFG_MSC_EXT) &&
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(csr_read(NDS_MMSC_CFG2) & MMSC_CFG2_RVARCH)) {
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if (csr_read(NDS_MRVARCH_CFG) & MRVARCH_CFG_SMEPMP) {
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return -ENOTSUP;
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}
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}
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}
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}
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K_SPINLOCK(&lock) {
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ret |= nds_l1i_cache_all(K_CACHE_INVD);
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}
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return ret;
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}
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int cache_instr_invd_range(void *addr, size_t size)
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{
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unsigned long ret = 0;
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if (IS_ENABLED(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)) {
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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K_SPINLOCK(&lock) {
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ret |= nds_l1i_cache_range(addr, size, K_CACHE_INVD);
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}
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return ret;
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}
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int cache_data_flush_all(void)
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{
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unsigned long ret = 0;
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_inclusive) {
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ret |= nds_l2_cache_all(K_CACHE_WB);
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} else {
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ret |= nds_l1d_cache_all(K_CACHE_WB);
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ret |= nds_l2_cache_all(K_CACHE_WB);
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}
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}
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return ret;
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}
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int cache_data_flush_range(void *addr, size_t size)
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{
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unsigned long ret = 0;
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_inclusive) {
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ret |= nds_l2_cache_range(addr, size, K_CACHE_WB);
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} else {
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ret |= nds_l1d_cache_range(addr, size, K_CACHE_WB);
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ret |= nds_l2_cache_range(addr, size, K_CACHE_WB);
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}
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}
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return ret;
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}
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int cache_data_flush_and_invd_all(void)
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{
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unsigned long ret = 0;
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_size) {
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if (cache_cfg.l2_cache_inclusive) {
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ret |= nds_l2_cache_all(K_CACHE_WB_INVD);
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} else {
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ret |= nds_l1d_cache_all(K_CACHE_WB);
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ret |= nds_l2_cache_all(K_CACHE_WB_INVD);
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ret |= nds_l1d_cache_all(K_CACHE_INVD);
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}
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} else {
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ret |= nds_l1d_cache_all(K_CACHE_WB_INVD);
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}
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}
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return ret;
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}
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int cache_data_flush_and_invd_range(void *addr, size_t size)
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{
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unsigned long ret = 0;
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K_SPINLOCK(&lock) {
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if (cache_cfg.l2_cache_size) {
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if (cache_cfg.l2_cache_inclusive) {
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ret |= nds_l2_cache_range(addr, size, K_CACHE_WB_INVD);
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} else {
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ret |= nds_l1d_cache_range(addr, size, K_CACHE_WB);
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ret |= nds_l2_cache_range(addr, size, K_CACHE_WB_INVD);
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ret |= nds_l1d_cache_range(addr, size, K_CACHE_INVD);
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}
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} else {
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ret |= nds_l1d_cache_range(addr, size, K_CACHE_WB_INVD);
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}
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}
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return ret;
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}
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int cache_instr_flush_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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#if IS_ENABLED(CONFIG_DCACHE_LINE_SIZE_DETECT)
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size_t cache_data_line_size_get(void)
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{
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return cache_cfg.data_line_size;
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}
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#endif /* IS_ENABLED(CONFIG_DCACHE_LINE_SIZE_DETECT) */
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#if IS_ENABLED(CONFIG_ICACHE_LINE_SIZE_DETECT)
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size_t cache_instr_line_size_get(void)
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{
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return cache_cfg.instr_line_size;
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}
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#endif /* IS_ENABLED(CONFIG_ICACHE_LINE_SIZE_DETECT) */
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static int andes_cache_init(void)
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{
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unsigned long line_size;
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if (IS_ENABLED(CONFIG_ICACHE)) {
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line_size = (csr_read(NDS_MICM_CFG) >> MICM_CFG_ISZ_SHIFT) & BIT_MASK(3);
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if (line_size == 0) {
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LOG_ERR("Platform doesn't support I-cache, "
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"please disable CONFIG_ICACHE");
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}
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#if IS_ENABLED(CONFIG_ICACHE_LINE_SIZE_DETECT)
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/* Icache line size */
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if (line_size <= 5) {
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cache_cfg.instr_line_size = 1 << (line_size + 2);
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} else {
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LOG_ERR("Unknown line size of I-cache");
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|
}
|
|
#elif (CONFIG_ICACHE_LINE_SIZE != 0)
|
|
cache_cfg.instr_line_size = CONFIG_ICACHE_LINE_SIZE;
|
|
#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), i_cache_line_size)
|
|
cache_cfg.instr_line_size =
|
|
DT_PROP(DT_PATH(cpus, cpu_0), "i_cache_line_size");
|
|
#else
|
|
LOG_ERR("Please specific the i-cache-line-size "
|
|
"CPU0 property of the DT");
|
|
#endif /* IS_ENABLED(CONFIG_ICACHE_LINE_SIZE_DETECT) */
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_DCACHE)) {
|
|
line_size = (csr_read(NDS_MDCM_CFG) >> MDCM_CFG_DSZ_SHIFT) & BIT_MASK(3);
|
|
if (line_size == 0) {
|
|
LOG_ERR("Platform doesn't support D-cache, "
|
|
"please disable CONFIG_DCACHE");
|
|
}
|
|
#if IS_ENABLED(CONFIG_DCACHE_LINE_SIZE_DETECT)
|
|
/* Dcache line size */
|
|
if (line_size <= 5) {
|
|
cache_cfg.data_line_size = 1 << (line_size + 2);
|
|
} else {
|
|
LOG_ERR("Unknown line size of D-cache");
|
|
}
|
|
#elif (CONFIG_DCACHE_LINE_SIZE != 0)
|
|
cache_cfg.data_line_size = CONFIG_DCACHE_LINE_SIZE;
|
|
#elif DT_NODE_HAS_PROP(DT_PATH(cpus, cpu_0), d_cache_line_size)
|
|
cache_cfg.data_line_size =
|
|
DT_PROP(DT_PATH(cpus, cpu_0), "d_cache_line_size");
|
|
#else
|
|
LOG_ERR("Please specific the d-cache-line-size "
|
|
"CPU0 property of the DT");
|
|
#endif /* IS_ENABLED(CONFIG_DCACHE_LINE_SIZE_DETECT) */
|
|
}
|
|
|
|
if (!(csr_read(NDS_MMSC_CFG) & MMSC_CFG_CCTLCSR)) {
|
|
LOG_ERR("Platform doesn't support I/D cache operation");
|
|
}
|
|
|
|
if (csr_read(NDS_MMSC_CFG) & MMSC_CFG_VCCTL_2) {
|
|
if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
|
|
csr_set(NDS_MCACHE_CTL, MCACHE_CTL_CCTL_SUEN);
|
|
}
|
|
}
|
|
|
|
cache_cfg.l2_cache_size = nds_l2_cache_init();
|
|
cache_cfg.l2_cache_inclusive = nds_l2_cache_is_inclusive();
|
|
|
|
return 0;
|
|
}
|
|
|
|
SYS_INIT(andes_cache_init, PRE_KERNEL_1, CONFIG_CACHE_ANDES_INIT_PRIORITY);
|