zephyr/arch/xtensa
Andy Ross 3aeefd2250 arch/xtensa: Add automatic vector linkage generation
Existing solutions for linking the Xtensa vector table are a
cut-and-paste mess of inherited code, with more than a dozen special
sections that need to be linked into many special MEMORY{} regions.

Accept the existing convention used by C/asm code, but automatically
detect the needed offsets for the platform from core-isa.h (it can
share the preprocessing with gen_zsr.py) and emit a file that can be
included in lieu of all the existing boilerplate.

Signed-off-by: Andy Ross <andyross@google.com>
2024-05-22 13:39:47 -05:00
..
core arch/xtensa: Add automatic vector linkage generation 2024-05-22 13:39:47 -05:00
include xtensa: mmu: Avoid k_mem_domain_default duplication 2024-05-14 15:54:55 +02:00
CMakeLists.txt
Kconfig arch/xtensa: Automatically generate interrupt handlers (finally) 2024-05-20 20:50:55 -04:00