775 lines
19 KiB
C
775 lines
19 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for UART port on STM32 family processor.
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*
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <soc.h>
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#include <init.h>
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#include <uart.h>
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#include <clock_control.h>
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#include <linker/sections.h>
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#include <clock_control/stm32_clock_control.h>
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#include "uart_stm32.h"
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct uart_stm32_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct uart_stm32_data * const)(dev)->driver_data)
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#define UART_STRUCT(dev) \
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((USART_TypeDef *)(DEV_CFG(dev))->uconf.base)
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#define TIMEOUT 1000
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static void uart_stm32_usart_set_baud_rate(struct device *dev,
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u32_t clock_rate, u32_t baud_rate)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_SetBaudRate(UartInstance,
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clock_rate,
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#ifdef USART_PRESC_PRESCALER
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LL_USART_PRESCALER_DIV1,
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#endif
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#ifdef USART_CR1_OVER8
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LL_USART_OVERSAMPLING_16,
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#endif
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baud_rate);
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}
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#ifdef CONFIG_LPUART_1
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static void uart_stm32_lpuart_set_baud_rate(struct device *dev,
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u32_t clock_rate, u32_t baud_rate)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_LPUART_SetBaudRate(UartInstance,
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clock_rate,
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#ifdef USART_PRESC_PRESCALER
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LL_USART_PRESCALER_DIV1,
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#endif
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baud_rate);
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}
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#endif /* CONFIG_LPUART_1 */
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static inline void uart_stm32_set_baudrate(struct device *dev, u32_t baud_rate)
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{
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const struct uart_stm32_config *config = DEV_CFG(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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#ifdef CONFIG_LPUART_1
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#endif
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u32_t clock_rate;
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/* Get clock rate */
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clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&config->pclken,
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&clock_rate);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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uart_stm32_lpuart_set_baud_rate(dev, clock_rate, baud_rate);
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} else {
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uart_stm32_usart_set_baud_rate(dev, clock_rate, baud_rate);
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}
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#else
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uart_stm32_usart_set_baud_rate(dev, clock_rate, baud_rate);
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#endif
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}
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static inline void uart_stm32_set_parity(struct device *dev, u32_t parity)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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LL_LPUART_SetParity(UartInstance, parity);
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} else {
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LL_USART_SetParity(UartInstance, parity);
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}
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#else
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LL_USART_SetParity(UartInstance, parity);
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#endif /* CONFIG_LPUART_1 */
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}
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static inline u32_t uart_stm32_get_parity(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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return LL_LPUART_GetParity(UartInstance);
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} else {
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return LL_USART_GetParity(UartInstance);
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}
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#else
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return LL_USART_GetParity(UartInstance);
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#endif /* CONFIG_LPUART_1 */
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}
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static inline void uart_stm32_set_stopbits(struct device *dev, u32_t stopbits)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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LL_LPUART_SetStopBitsLength(UartInstance, stopbits);
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} else {
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LL_USART_SetStopBitsLength(UartInstance, stopbits);
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}
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#else
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LL_USART_SetStopBitsLength(UartInstance, stopbits);
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#endif /* CONFIG_LPUART_1 */
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}
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static inline u32_t uart_stm32_get_stopbits(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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return LL_LPUART_GetStopBitsLength(UartInstance);
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} else {
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return LL_USART_GetStopBitsLength(UartInstance);
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}
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#else
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return LL_USART_GetStopBitsLength(UartInstance);
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#endif /* CONFIG_LPUART_1 */
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}
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static inline void uart_stm32_set_databits(struct device *dev, u32_t databits)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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LL_LPUART_SetDataWidth(UartInstance, databits);
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} else {
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LL_USART_SetDataWidth(UartInstance, databits);
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}
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#else
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LL_USART_SetDataWidth(UartInstance, databits);
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#endif /* CONFIG_LPUART_1 */
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}
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static inline u32_t uart_stm32_get_databits(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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#ifdef CONFIG_LPUART_1
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if (IS_LPUART_INSTANCE(UartInstance)) {
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return LL_LPUART_GetDataWidth(UartInstance);
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} else {
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return LL_USART_GetDataWidth(UartInstance);
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}
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#else
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return LL_USART_GetDataWidth(UartInstance);
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#endif /* CONFIG_LPUART_1 */
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}
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static inline u32_t uart_stm32_cfg2ll_parity(enum uart_config_parity parity)
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{
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switch (parity) {
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case UART_CFG_PARITY_ODD:
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return LL_USART_PARITY_ODD;
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case UART_CFG_PARITY_EVEN:
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return LL_USART_PARITY_EVEN;
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case UART_CFG_PARITY_NONE:
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default:
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return LL_USART_PARITY_NONE;
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}
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}
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static inline enum uart_config_parity uart_stm32_ll2cfg_parity(u32_t parity)
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{
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switch (parity) {
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case LL_USART_PARITY_ODD:
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return UART_CFG_PARITY_ODD;
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case LL_USART_PARITY_EVEN:
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return UART_CFG_PARITY_EVEN;
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case LL_USART_PARITY_NONE:
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default:
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return UART_CFG_PARITY_NONE;
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}
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}
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static inline u32_t uart_stm32_cfg2ll_stopbits(enum uart_config_stop_bits sb)
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{
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switch (sb) {
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/* Some MCU's don't support 0.5 stop bits */
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#ifdef LL_USART_STOPBITS_0_5
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case UART_CFG_STOP_BITS_0_5:
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return LL_USART_STOPBITS_0_5;
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#endif /* LL_USART_STOPBITS_0_5 */
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case UART_CFG_STOP_BITS_1:
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return LL_USART_STOPBITS_1;
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/* Some MCU's don't support 1.5 stop bits */
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#ifdef LL_USART_STOPBITS_1_5
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case UART_CFG_STOP_BITS_1_5:
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return LL_USART_STOPBITS_1_5;
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#endif /* LL_USART_STOPBITS_1_5 */
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case UART_CFG_STOP_BITS_2:
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default:
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return LL_USART_STOPBITS_2;
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}
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}
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static inline enum uart_config_stop_bits uart_stm32_ll2cfg_stopbits(u32_t sb)
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{
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switch (sb) {
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/* Some MCU's don't support 0.5 stop bits */
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#ifdef LL_USART_STOPBITS_0_5
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case LL_USART_STOPBITS_0_5:
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return UART_CFG_STOP_BITS_0_5;
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#endif /* LL_USART_STOPBITS_0_5 */
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case LL_USART_STOPBITS_1:
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return UART_CFG_STOP_BITS_1;
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/* Some MCU's don't support 1.5 stop bits */
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#ifdef LL_USART_STOPBITS_1_5
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case LL_USART_STOPBITS_1_5:
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return UART_CFG_STOP_BITS_1_5;
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#endif /* LL_USART_STOPBITS_1_5 */
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case LL_USART_STOPBITS_2:
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default:
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return UART_CFG_STOP_BITS_2;
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}
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}
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static inline u32_t uart_stm32_cfg2ll_databits(enum uart_config_data_bits db)
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{
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switch (db) {
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/* Some MCU's don't support 7B datawidth */
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#ifdef LL_USART_DATAWIDTH_7B
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case UART_CFG_DATA_BITS_7:
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return LL_USART_DATAWIDTH_7B;
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#endif /* LL_USART_DATAWIDTH_7B */
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case UART_CFG_DATA_BITS_8:
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default:
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return LL_USART_DATAWIDTH_8B;
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}
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}
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static inline enum uart_config_data_bits uart_stm32_ll2cfg_databits(u32_t db)
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{
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switch (db) {
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/* Some MCU's don't support 7B datawidth */
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#ifdef LL_USART_DATAWIDTH_7B
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case LL_USART_DATAWIDTH_7B:
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return UART_CFG_DATA_BITS_7;
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#endif /* LL_USART_DATAWIDTH_7B */
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case LL_USART_DATAWIDTH_8B:
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default:
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return UART_CFG_DATA_BITS_8;
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}
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}
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static int uart_stm32_configure(struct device *dev,
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const struct uart_config *cfg)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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const u32_t parity = uart_stm32_cfg2ll_parity(cfg->parity);
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const u32_t stopbits = uart_stm32_cfg2ll_stopbits(cfg->stop_bits);
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const u32_t databits = uart_stm32_cfg2ll_databits(cfg->data_bits);
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/* Hardware doesn't support mark or space parity */
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if ((UART_CFG_PARITY_MARK == cfg->parity) ||
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(UART_CFG_PARITY_SPACE == cfg->parity)) {
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return -ENOTSUP;
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}
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#if defined(LL_USART_STOPBITS_0_5) && defined(CONFIG_LPUART_1)
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if (IS_LPUART_INSTANCE(UartInstance) &&
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UART_CFG_STOP_BITS_0_5 == cfg->stop_bits) {
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return -ENOTSUP;
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}
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#else
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if (UART_CFG_STOP_BITS_0_5 == cfg->stop_bits) {
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return -ENOTSUP;
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}
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#endif
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#if defined(LL_USART_STOPBITS_1_5) && defined(CONFIG_LPUART_1)
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if (IS_LPUART_INSTANCE(UartInstance) &&
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UART_CFG_STOP_BITS_1_5 == cfg->stop_bits) {
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return -ENOTSUP;
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}
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#else
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if (UART_CFG_STOP_BITS_1_5 == cfg->stop_bits) {
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return -ENOTSUP;
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}
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#endif
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/* Driver doesn't support 5 or 6 databits and potentially 7 */
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if ((UART_CFG_DATA_BITS_5 == cfg->data_bits) ||
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(UART_CFG_DATA_BITS_6 == cfg->data_bits)
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#ifndef LL_USART_DATAWIDTH_7B
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|| (UART_CFG_DATA_BITS_7 == cfg->data_bits)
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#endif /* LL_USART_DATAWIDTH_7B */
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) {
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return -ENOTSUP;
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}
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/* Driver currently doesn't support line ctrl */
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if (UART_CFG_FLOW_CTRL_NONE != cfg->flow_ctrl) {
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return -ENOTSUP;
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}
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LL_USART_Disable(UartInstance);
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if (parity != uart_stm32_get_parity(dev)) {
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uart_stm32_set_parity(dev, parity);
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}
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if (stopbits != uart_stm32_get_stopbits(dev)) {
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uart_stm32_set_stopbits(dev, stopbits);
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}
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if (databits != uart_stm32_get_databits(dev)) {
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uart_stm32_set_databits(dev, databits);
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}
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if (cfg->baudrate != data->baud_rate) {
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uart_stm32_set_baudrate(dev, cfg->baudrate);
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data->baud_rate = cfg->baudrate;
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}
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LL_USART_Enable(UartInstance);
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return 0;
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};
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static int uart_stm32_config_get(struct device *dev, struct uart_config *cfg)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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cfg->baudrate = data->baud_rate;
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cfg->parity = uart_stm32_ll2cfg_parity(uart_stm32_get_parity(dev));
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cfg->stop_bits = uart_stm32_ll2cfg_stopbits(
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uart_stm32_get_stopbits(dev));
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cfg->data_bits = uart_stm32_ll2cfg_databits(
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uart_stm32_get_databits(dev));
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cfg->flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
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return 0;
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}
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static int uart_stm32_poll_in(struct device *dev, unsigned char *c)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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/* Clear overrun error flag */
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if (LL_USART_IsActiveFlag_ORE(UartInstance)) {
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LL_USART_ClearFlag_ORE(UartInstance);
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}
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if (!LL_USART_IsActiveFlag_RXNE(UartInstance)) {
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return -1;
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}
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*c = (unsigned char)LL_USART_ReceiveData8(UartInstance);
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return 0;
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}
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static void uart_stm32_poll_out(struct device *dev,
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unsigned char c)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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/* Wait for TXE flag to be raised */
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while (!LL_USART_IsActiveFlag_TXE(UartInstance))
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;
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LL_USART_ClearFlag_TC(UartInstance);
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LL_USART_TransmitData8(UartInstance, (u8_t)c);
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}
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static inline void __uart_stm32_get_clock(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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data->clock = clk;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_stm32_fifo_fill(struct device *dev, const u8_t *tx_data,
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int size)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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u8_t num_tx = 0U;
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while ((size - num_tx > 0) &&
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LL_USART_IsActiveFlag_TXE(UartInstance)) {
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/* TXE flag will be cleared with byte write to DR register */
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/* Send a character (8bit , parity none) */
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LL_USART_TransmitData8(UartInstance, tx_data[num_tx++]);
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}
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return num_tx;
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}
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static int uart_stm32_fifo_read(struct device *dev, u8_t *rx_data,
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const int size)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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u8_t num_rx = 0U;
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while ((size - num_rx > 0) &&
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LL_USART_IsActiveFlag_RXNE(UartInstance)) {
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X) \
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|| defined(CONFIG_SOC_SERIES_STM32F2X)
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/* Clear the interrupt */
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LL_USART_ClearFlag_RXNE(UartInstance);
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#endif
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/* Receive a character (8bit , parity none) */
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rx_data[num_rx++] = LL_USART_ReceiveData8(UartInstance);
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/* Clear overrun error flag */
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if (LL_USART_IsActiveFlag_ORE(UartInstance)) {
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LL_USART_ClearFlag_ORE(UartInstance);
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}
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}
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return num_rx;
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}
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static void uart_stm32_irq_tx_enable(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_EnableIT_TC(UartInstance);
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}
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static void uart_stm32_irq_tx_disable(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_DisableIT_TC(UartInstance);
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}
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static int uart_stm32_irq_tx_ready(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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return LL_USART_IsActiveFlag_TXE(UartInstance);
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}
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static int uart_stm32_irq_tx_complete(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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return LL_USART_IsActiveFlag_TXE(UartInstance);
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}
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static void uart_stm32_irq_rx_enable(struct device *dev)
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{
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USART_TypeDef *UartInstance = UART_STRUCT(dev);
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LL_USART_EnableIT_RXNE(UartInstance);
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}
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static void uart_stm32_irq_rx_disable(struct device *dev)
|
|
{
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
LL_USART_DisableIT_RXNE(UartInstance);
|
|
}
|
|
|
|
static int uart_stm32_irq_rx_ready(struct device *dev)
|
|
{
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
return LL_USART_IsActiveFlag_RXNE(UartInstance);
|
|
}
|
|
|
|
static void uart_stm32_irq_err_enable(struct device *dev)
|
|
{
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
/* Enable FE, ORE interruptions */
|
|
LL_USART_EnableIT_ERROR(UartInstance);
|
|
#if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT)
|
|
/* Enable Line break detection */
|
|
if (IS_UART_LIN_INSTANCE(UartInstance)) {
|
|
LL_USART_EnableIT_LBD(UartInstance);
|
|
}
|
|
#endif
|
|
/* Enable parity error interruption */
|
|
LL_USART_EnableIT_PE(UartInstance);
|
|
}
|
|
|
|
static void uart_stm32_irq_err_disable(struct device *dev)
|
|
{
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
/* Disable FE, ORE interruptions */
|
|
LL_USART_DisableIT_ERROR(UartInstance);
|
|
#if !defined(CONFIG_SOC_SERIES_STM32F0X) || defined(USART_LIN_SUPPORT)
|
|
/* Disable Line break detection */
|
|
if (IS_UART_LIN_INSTANCE(UartInstance)) {
|
|
LL_USART_DisableIT_LBD(UartInstance);
|
|
}
|
|
#endif
|
|
/* Disable parity error interruption */
|
|
LL_USART_DisableIT_PE(UartInstance);
|
|
}
|
|
|
|
static int uart_stm32_irq_is_pending(struct device *dev)
|
|
{
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
return ((LL_USART_IsActiveFlag_RXNE(UartInstance) &&
|
|
LL_USART_IsEnabledIT_RXNE(UartInstance)) ||
|
|
(LL_USART_IsActiveFlag_TC(UartInstance) &&
|
|
LL_USART_IsEnabledIT_TC(UartInstance)));
|
|
}
|
|
|
|
static int uart_stm32_irq_update(struct device *dev)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
static void uart_stm32_irq_callback_set(struct device *dev,
|
|
uart_irq_callback_user_data_t cb,
|
|
void *cb_data)
|
|
{
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
|
|
data->user_cb = cb;
|
|
data->user_data = cb_data;
|
|
}
|
|
|
|
static void uart_stm32_isr(void *arg)
|
|
{
|
|
struct device *dev = arg;
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
|
|
if (data->user_cb) {
|
|
data->user_cb(data->user_data);
|
|
}
|
|
}
|
|
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
|
|
static const struct uart_driver_api uart_stm32_driver_api = {
|
|
.poll_in = uart_stm32_poll_in,
|
|
.poll_out = uart_stm32_poll_out,
|
|
.configure = uart_stm32_configure,
|
|
.config_get = uart_stm32_config_get,
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
.fifo_fill = uart_stm32_fifo_fill,
|
|
.fifo_read = uart_stm32_fifo_read,
|
|
.irq_tx_enable = uart_stm32_irq_tx_enable,
|
|
.irq_tx_disable = uart_stm32_irq_tx_disable,
|
|
.irq_tx_ready = uart_stm32_irq_tx_ready,
|
|
.irq_tx_complete = uart_stm32_irq_tx_complete,
|
|
.irq_rx_enable = uart_stm32_irq_rx_enable,
|
|
.irq_rx_disable = uart_stm32_irq_rx_disable,
|
|
.irq_rx_ready = uart_stm32_irq_rx_ready,
|
|
.irq_err_enable = uart_stm32_irq_err_enable,
|
|
.irq_err_disable = uart_stm32_irq_err_disable,
|
|
.irq_is_pending = uart_stm32_irq_is_pending,
|
|
.irq_update = uart_stm32_irq_update,
|
|
.irq_callback_set = uart_stm32_irq_callback_set,
|
|
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
|
};
|
|
|
|
/**
|
|
* @brief Initialize UART channel
|
|
*
|
|
* This routine is called to reset the chip in a quiescent state.
|
|
* It is assumed that this function is called only once per UART.
|
|
*
|
|
* @param dev UART device struct
|
|
*
|
|
* @return 0
|
|
*/
|
|
static int uart_stm32_init(struct device *dev)
|
|
{
|
|
const struct uart_stm32_config *config = DEV_CFG(dev);
|
|
struct uart_stm32_data *data = DEV_DATA(dev);
|
|
USART_TypeDef *UartInstance = UART_STRUCT(dev);
|
|
|
|
__uart_stm32_get_clock(dev);
|
|
/* enable clock */
|
|
if (clock_control_on(data->clock,
|
|
(clock_control_subsys_t *)&config->pclken) != 0) {
|
|
return -EIO;
|
|
}
|
|
|
|
LL_USART_Disable(UartInstance);
|
|
|
|
/* TX/RX direction */
|
|
LL_USART_SetTransferDirection(UartInstance,
|
|
LL_USART_DIRECTION_TX_RX);
|
|
|
|
/* 8 data bit, 1 start bit, 1 stop bit, no parity */
|
|
LL_USART_ConfigCharacter(UartInstance,
|
|
LL_USART_DATAWIDTH_8B,
|
|
LL_USART_PARITY_NONE,
|
|
LL_USART_STOPBITS_1);
|
|
|
|
/* Set the default baudrate */
|
|
uart_stm32_set_baudrate(dev, data->baud_rate);
|
|
|
|
LL_USART_Enable(UartInstance);
|
|
|
|
#ifdef USART_ISR_TEACK
|
|
/* Wait until TEACK flag is set */
|
|
while (!(LL_USART_IsActiveFlag_TEACK(UartInstance)))
|
|
;
|
|
#endif /* !USART_ISR_TEACK */
|
|
|
|
#ifdef USART_ISR_REACK
|
|
/* Wait until REACK flag is set */
|
|
while (!(LL_USART_IsActiveFlag_REACK(UartInstance)))
|
|
;
|
|
#endif /* !USART_ISR_REACK */
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
config->uconf.irq_config_func(dev);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
|
#define STM32_UART_IRQ_HANDLER_DECL(name) \
|
|
static void uart_stm32_irq_config_func_##name(struct device *dev)
|
|
#define STM32_UART_IRQ_HANDLER_FUNC(name) \
|
|
.irq_config_func = uart_stm32_irq_config_func_##name,
|
|
#define STM32_UART_IRQ_HANDLER(name) \
|
|
static void uart_stm32_irq_config_func_##name(struct device *dev) \
|
|
{ \
|
|
IRQ_CONNECT(DT_##name##_IRQ, \
|
|
DT_UART_STM32_##name##_IRQ_PRI, \
|
|
uart_stm32_isr, DEVICE_GET(uart_stm32_##name), \
|
|
0); \
|
|
irq_enable(DT_##name##_IRQ); \
|
|
}
|
|
#else
|
|
#define STM32_UART_IRQ_HANDLER_DECL(name)
|
|
#define STM32_UART_IRQ_HANDLER_FUNC(name)
|
|
#define STM32_UART_IRQ_HANDLER(name)
|
|
#endif
|
|
|
|
#define STM32_UART_INIT(name) \
|
|
STM32_UART_IRQ_HANDLER_DECL(name); \
|
|
\
|
|
static const struct uart_stm32_config uart_stm32_cfg_##name = { \
|
|
.uconf = { \
|
|
.base = (u8_t *)DT_UART_STM32_##name##_BASE_ADDRESS,\
|
|
STM32_UART_IRQ_HANDLER_FUNC(name) \
|
|
}, \
|
|
.pclken = { .bus = DT_UART_STM32_##name##_CLOCK_BUS, \
|
|
.enr = DT_UART_STM32_##name##_CLOCK_BITS \
|
|
}, \
|
|
}; \
|
|
\
|
|
static struct uart_stm32_data uart_stm32_data_##name = { \
|
|
.baud_rate = DT_UART_STM32_##name##_BAUD_RATE \
|
|
}; \
|
|
\
|
|
DEVICE_AND_API_INIT(uart_stm32_##name, DT_UART_STM32_##name##_NAME, \
|
|
&uart_stm32_init, \
|
|
&uart_stm32_data_##name, &uart_stm32_cfg_##name, \
|
|
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
|
|
&uart_stm32_driver_api); \
|
|
\
|
|
STM32_UART_IRQ_HANDLER(name)
|
|
|
|
|
|
#ifdef CONFIG_UART_1
|
|
STM32_UART_INIT(USART_1)
|
|
#endif /* CONFIG_UART_1 */
|
|
|
|
#ifdef CONFIG_UART_2
|
|
STM32_UART_INIT(USART_2)
|
|
#endif /* CONFIG_UART_2 */
|
|
|
|
#ifdef CONFIG_UART_3
|
|
STM32_UART_INIT(USART_3)
|
|
#endif /* CONFIG_UART_3 */
|
|
|
|
#ifdef CONFIG_UART_6
|
|
STM32_UART_INIT(USART_6)
|
|
#endif /* CONFIG_UART_6 */
|
|
|
|
/*
|
|
* STM32F0 and STM32L0 series differ from other STM32 series by some
|
|
* peripheral names (UART vs USART).
|
|
*/
|
|
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
|
|
|
|
#ifdef CONFIG_UART_4
|
|
STM32_UART_INIT(USART_4)
|
|
#endif /* CONFIG_UART_4 */
|
|
|
|
#ifdef CONFIG_UART_5
|
|
STM32_UART_INIT(USART_5)
|
|
#endif /* CONFIG_UART_5 */
|
|
|
|
/* Following devices are not available in L0 series (for now)
|
|
* But keeping them simplifies ifdefery and won't harm
|
|
*/
|
|
|
|
#ifdef CONFIG_UART_7
|
|
STM32_UART_INIT(USART_7)
|
|
#endif /* CONFIG_UART_7 */
|
|
|
|
#ifdef CONFIG_UART_8
|
|
STM32_UART_INIT(USART_8)
|
|
#endif /* CONFIG_UART_8 */
|
|
|
|
#else
|
|
|
|
#ifdef CONFIG_UART_4
|
|
STM32_UART_INIT(UART_4)
|
|
#endif /* CONFIG_UART_4 */
|
|
|
|
#ifdef CONFIG_UART_5
|
|
STM32_UART_INIT(UART_5)
|
|
#endif /* CONFIG_UART_5 */
|
|
|
|
#ifdef CONFIG_UART_7
|
|
STM32_UART_INIT(UART_7)
|
|
#endif /* CONFIG_UART_7 */
|
|
|
|
#ifdef CONFIG_UART_8
|
|
STM32_UART_INIT(UART_8)
|
|
#endif /* CONFIG_UART_8 */
|
|
|
|
#ifdef CONFIG_UART_9
|
|
STM32_UART_INIT(UART_9)
|
|
#endif /* CONFIG_UART_9 */
|
|
|
|
#ifdef CONFIG_UART_10
|
|
STM32_UART_INIT(UART_10)
|
|
#endif /* CONFIG_UART_10 */
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32L0X)
|
|
#ifdef CONFIG_LPUART_1
|
|
STM32_UART_INIT(LPUART_1)
|
|
#endif /* CONFIG_LPUART_1 */
|
|
#endif
|