241 lines
5.3 KiB
Plaintext
241 lines
5.3 KiB
Plaintext
# Kconfig - i.MX RT series
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "i.MX RT Selection"
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depends on SOC_SERIES_IMX_RT
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config SOC_MIMXRT1021
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bool "SOC_MIMXRT1021"
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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select HAS_MCUX_ENET
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPUART
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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select INIT_ENET_PLL
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config SOC_MIMXRT1051
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bool "SOC_MIMXRT1051"
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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select HAS_MCUX_ENET
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPUART
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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config SOC_MIMXRT1052
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bool "SOC_MIMXRT1052"
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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select HAS_MCUX_ENET
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPUART
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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config SOC_MIMXRT1061
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bool "SOC_MIMXRT1061"
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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select HAS_MCUX_ENET
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPUART
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_MPU
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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config SOC_MIMXRT1062
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bool "SOC_MIMXRT1062"
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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select HAS_MCUX_ENET
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPUART
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_MPU
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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config SOC_MIMXRT1064
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bool "SOC_MIMXRT1064"
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select HAS_MCUX
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select HAS_MCUX_CCM
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select HAS_MCUX_ENET
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPUART
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select HAS_MCUX_TRNG
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select CPU_HAS_FPU
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select CPU_HAS_MPU
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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endchoice
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if SOC_SERIES_IMX_RT
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config SOC_PART_NUMBER_MIMXRT1021CAG4A
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bool
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config SOC_PART_NUMBER_MIMXRT1021CAF4A
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bool
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config SOC_PART_NUMBER_MIMXRT1021DAG5A
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bool
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config SOC_PART_NUMBER_MIMXRT1021DAF5A
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bool
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config SOC_PART_NUMBER_MIMXRT1051CVL5A
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bool
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config SOC_PART_NUMBER_MIMXRT1051DVL6A
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bool
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config SOC_PART_NUMBER_MIMXRT1052CVL5A
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bool
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config SOC_PART_NUMBER_MIMXRT1052DVL6A
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bool
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config SOC_PART_NUMBER_MIMXRT1061CVL5A
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bool
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config SOC_PART_NUMBER_MIMXRT1061DVL6A
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bool
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config SOC_PART_NUMBER_MIMXRT1062CVL5A
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bool
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config SOC_PART_NUMBER_MIMXRT1062DVL6A
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bool
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config SOC_PART_NUMBER_MIMXRT1064CVL5A
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bool
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config SOC_PART_NUMBER_MIMXRT1064DVL6A
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bool
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config SOC_PART_NUMBER_IMX_RT
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string
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default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
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default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
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default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
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default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A
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default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
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default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
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default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
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default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
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default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A
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default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A
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default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A
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default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
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default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
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default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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config INIT_ARM_PLL
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bool "Initialize ARM PLL"
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config INIT_SYS_PLL
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bool "Initialize SYS PLL"
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config INIT_USB1_PLL
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bool "Initialize USB1 PLL"
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config ARM_DIV
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int "ARM clock divider"
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range 0 7
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config AHB_DIV
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int "AHB clock divider"
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range 0 7
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config IPG_DIV
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int "IPG clock divider"
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range 0 3
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menuconfig NXP_IMX_RT_BOOT_HEADER
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bool "Enable the boot header"
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help
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Enable data structures required by the boot ROM to boot the
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application from an external flash device.
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if NXP_IMX_RT_BOOT_HEADER
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choice BOOT_DEVICE
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prompt "Boot device selection"
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default BOOT_FLEXSPI_NOR
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config BOOT_FLEXSPI_NOR
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bool "FlexSPI serial NOR"
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config BOOT_FLEXSPI_NAND
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bool "FlexSPI serial NAND"
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config BOOT_SEMC_NOR
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bool "SEMC parallel NOR"
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config BOOT_SEMC_NAND
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bool "SEMC parallel NAND"
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endchoice
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config IMAGE_VECTOR_TABLE_OFFSET
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hex "Image vector table offset"
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default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
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default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
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help
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The Image Vector Table (IVT) provides the boot ROM with pointers to
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the application entry point and device configuration data. The boot
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ROM reqiures a fixed IVT offset for each type of boot device.
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config DEVICE_CONFIGURATION_DATA
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bool "Enable device configuration data"
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help
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Device configuration data (DCD) provides a sequence of commmands to
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the boot ROM to initialize components such as an SDRAM.
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endif # NXP_IMX_RT_BOOT_HEADER
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endif # SOC_SERIES_IMX_RT
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