432 lines
9.8 KiB
Plaintext
432 lines
9.8 KiB
Plaintext
/*
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32vf103.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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clock-frequency = <DT_FREQ_M(108)>;
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compatible = "nuclei,bumblebee", "riscv";
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riscv,isa = "rv32imac_zicsr_zifencei";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&eclic>;
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ranges;
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systimer: timer@d1000000 {
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compatible = "nuclei,systimer";
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reg = <0xd1000000 0x10000>;
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interrupts = <3 0>, <7 0>;
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clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
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};
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eclic: interrupt-controller@d2000000 {
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compatible = "nuclei,eclic";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xd2000000 0x0001
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0xd2000004 0x0004
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0xd200000b 0x0001
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0xd2001000 0x1000>;
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};
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rcu: reset-clock-controller@40021000 {
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compatible = "gd,gd32-rcu";
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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status = "okay";
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};
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};
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fmc: flash-controller@40022000 {
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compatible = "gd,gd32-flash-controller";
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reg = <0x40022000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
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write-block-size = <2>;
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max-erase-time-ms = <300>;
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page-size = <DT_SIZE_K(1)>;
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};
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};
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usart0: serial@40013800 {
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compatible = "gd,gd32-usart";
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reg = <0x40013800 0x400>;
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interrupts = <56 0>;
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clocks = <&cctl GD32_CLOCK_USART0>;
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resets = <&rctl GD32_RESET_USART0>;
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status = "disabled";
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};
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usart1: serial@40004400 {
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compatible = "gd,gd32-usart";
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reg = <0x40004400 0x400>;
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interrupts = <57 0>;
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clocks = <&cctl GD32_CLOCK_USART1>;
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resets = <&rctl GD32_RESET_USART1>;
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status = "disabled";
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};
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usart2: serial@40004800 {
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compatible = "gd,gd32-usart";
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reg = <0x40004800 0x400>;
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interrupts = <58 0>;
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clocks = <&cctl GD32_CLOCK_USART2>;
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resets = <&rctl GD32_RESET_USART2>;
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status = "disabled";
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};
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uart3: serial@40004c00 {
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compatible = "gd,gd32-usart";
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reg = <0x40004c00 0x400>;
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interrupts = <71 0>;
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clocks = <&cctl GD32_CLOCK_UART3>;
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resets = <&rctl GD32_RESET_UART3>;
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status = "disabled";
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};
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uart4: serial@40005000 {
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compatible = "gd,gd32-usart";
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reg = <0x40005000 0x400>;
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interrupts = <72 0>;
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clocks = <&cctl GD32_CLOCK_UART4>;
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resets = <&rctl GD32_RESET_UART4>;
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status = "disabled";
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};
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adc0: adc@40012400 {
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compatible = "gd,gd32-adc";
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reg = <0x40012400 0x400>;
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interrupts = <37 0>;
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clocks = <&cctl GD32_CLOCK_ADC0>;
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resets = <&rctl GD32_RESET_ADC0>;
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channels = <16>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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adc1: adc@40012800 {
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compatible = "gd,gd32-adc";
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reg = <0x40012800 0x400>;
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interrupts = <37 0>;
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clocks = <&cctl GD32_CLOCK_ADC1>;
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resets = <&rctl GD32_RESET_ADC1>;
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channels = <16>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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dac: dac@40007400 {
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compatible = "gd,gd32-dac";
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reg = <0x40007400 0x400>;
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clocks = <&cctl GD32_CLOCK_DAC>;
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resets = <&rctl GD32_RESET_DAC>;
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num-channels = <2>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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i2c0: i2c@40005400 {
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compatible = "gd,gd32-i2c";
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reg = <0x40005400 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <50 0>, <51 0>;
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interrupt-names = "event", "error";
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clocks = <&cctl GD32_CLOCK_I2C0>;
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resets = <&rctl GD32_RESET_I2C0>;
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status = "disabled";
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};
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spi0: spi@40013000 {
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compatible = "gd,gd32-spi";
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reg = <0x40013000 0x400>;
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interrupts = <54 0>;
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clocks = <&cctl GD32_CLOCK_SPI0>;
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resets = <&rctl GD32_RESET_SPI0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@40003800 {
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compatible = "gd,gd32-spi";
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reg = <0x40003800 0x400>;
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interrupts = <55 0>;
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clocks = <&cctl GD32_CLOCK_SPI1>;
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resets = <&rctl GD32_RESET_SPI1>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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afio: afio@40010000 {
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compatible = "gd,gd32-afio";
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reg = <0x40010000 0x400>;
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clocks = <&cctl GD32_CLOCK_AFIO>;
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status = "okay";
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};
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exti: interrupt-controller@40010400 {
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compatible = "gd,gd32-exti";
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#address-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x40010400 0x400>;
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num-lines = <19>;
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interrupts = <25 0>, <26 0>, <27 0>, <28 0>, <29 0>,
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<42 0>, <59 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5-9", "line10-15";
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status = "okay";
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};
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fwdgt: watchdog@40003000 {
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compatible = "gd,gd32-fwdgt";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdgt: watchdog@40002c00 {
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compatible = "gd,gd32-wwdgt";
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reg = <0x40002C00 0x400>;
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clocks = <&cctl GD32_CLOCK_WWDGT>;
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resets = <&rctl GD32_RESET_WWDGT>;
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interrupts = <0 0>;
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status = "disabled";
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};
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pinctrl: pin-controller@40010800 {
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compatible = "gd,gd32-pinctrl-afio";
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reg = <0x40010800 0x1c00>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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gpioa: gpio@40010800 {
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compatible = "gd,gd32-gpio";
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reg = <0x40010800 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&cctl GD32_CLOCK_GPIOA>;
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resets = <&rctl GD32_RESET_GPIOA>;
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status = "disabled";
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};
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gpiob: gpio@40010c00 {
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compatible = "gd,gd32-gpio";
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reg = <0x40010c00 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&cctl GD32_CLOCK_GPIOB>;
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resets = <&rctl GD32_RESET_GPIOB>;
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status = "disabled";
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};
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gpioc: gpio@40011000 {
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compatible = "gd,gd32-gpio";
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reg = <0x40011000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&cctl GD32_CLOCK_GPIOC>;
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resets = <&rctl GD32_RESET_GPIOC>;
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status = "disabled";
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};
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gpiod: gpio@40011400 {
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compatible = "gd,gd32-gpio";
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reg = <0x40011400 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&cctl GD32_CLOCK_GPIOD>;
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resets = <&rctl GD32_RESET_GPIOD>;
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status = "disabled";
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};
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gpioe: gpio@40011800 {
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compatible = "gd,gd32-gpio";
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reg = <0x40011800 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&cctl GD32_CLOCK_GPIOE>;
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resets = <&rctl GD32_RESET_GPIOE>;
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status = "disabled";
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};
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};
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timer0: timer@40012c00 {
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compatible = "gd,gd32-timer";
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reg = <0x40012c00 0x400>;
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interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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clocks = <&cctl GD32_CLOCK_TIMER0>;
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resets = <&rctl GD32_RESET_TIMER0>;
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is-advanced;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer1: timer@40000000 {
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compatible = "gd,gd32-timer";
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reg = <0x40000000 0x400>;
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interrupts = <47 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER1>;
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resets = <&rctl GD32_RESET_TIMER1>;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer2: timer@40000400 {
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compatible = "gd,gd32-timer";
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reg = <0x40000400 0x400>;
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interrupts = <48 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER2>;
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resets = <&rctl GD32_RESET_TIMER2>;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer3: timer@40000800 {
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compatible = "gd,gd32-timer";
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reg = <0x40000800 0x400>;
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interrupts = <49 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER3>;
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resets = <&rctl GD32_RESET_TIMER3>;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer4: timer@40000c00 {
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compatible = "gd,gd32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <69 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER4>;
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resets = <&rctl GD32_RESET_TIMER4>;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer5: timer@40001000 {
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compatible = "gd,gd32-timer";
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reg = <0x40001000 0x400>;
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interrupts = <73 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER5>;
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resets = <&rctl GD32_RESET_TIMER5>;
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channels = <0>;
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status = "disabled";
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};
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timer6: timer@40001400 {
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compatible = "gd,gd32-timer";
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reg = <0x40001400 0x400>;
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interrupts = <74 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER6>;
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resets = <&rctl GD32_RESET_TIMER6>;
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channels = <0>;
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status = "disabled";
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};
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dma0: dma@40020000 {
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compatible = "gd,gd32-dma";
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reg = <0x40020000 0x400>;
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interrupts = <30 0>, <31 0>, <32 0>, <33 0>,
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<34 0>, <35 0>, <36 0>;
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clocks = <&cctl GD32_CLOCK_DMA0>;
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dma-channels = <7>;
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gd,mem2mem;
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#dma-cells = <2>;
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status = "disabled";
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};
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dma1: dma@40020400 {
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compatible = "gd,gd32-dma";
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reg = <0x40020400 0x400>;
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interrupts = <75 0>, <76 0>, <77 0>, <78 0>,
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<79 0>;
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clocks = <&cctl GD32_CLOCK_DMA1>;
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dma-channels = <5>;
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gd,mem2mem;
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#dma-cells = <2>;
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status = "disabled";
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};
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};
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};
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