151 lines
5.2 KiB
YAML
151 lines
5.2 KiB
YAML
# Copyright (c) 2022, Basalte bv
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Atmel Static Memory Controller (SMC).
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The SMC allows to interface with static-memory mapped external devices such as
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SRAM, PSRAM, PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
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The SMC is clocked through the Master Clock (MCK) which is controlled by the
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Power Management Controller (PMC).
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The SMC controller can have up to 4 children defining the connected external
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memory devices. The reg property is set to the device's Chip Select.
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Device Tree example taken from the sam4_xplained board:
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&smc {
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status = "okay";
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pinctrl-0 = <&smc_default>;
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pinctrl-names = "default";
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is66wv51216dbll@0 {
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reg = <0>;
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atmel,smc-write-mode = "nwe";
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atmel,smc-read-mode = "nrd";
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atmel,smc-setup-timing = <1 1 1 1>;
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atmel,smc-pulse-timing = <6 6 6 6>;
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atmel,smc-cycle-timing = <7 7>;
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};
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};
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The above example configures a is66wv51216dbll-55 device. The device is a
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low power static RAM which uses NWE and NRD signals connected to the WE
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and OE inputs respectively. Assuming that MCK is 120MHz (cpu at full speed)
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each MCK cycle will be equivalent to 8ns. Since the memory full cycle is
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55ns, as per specification, it requires atmel,smc-cycle-timing of at least
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7 pulses (56ns). The atmel,smc-cycle-timing is composed of three parts:
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setup, pulse and hold. The setup is used to address the memory. The pulse
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is the time used to read/write. The hold is used to release memory. For the
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is66wv51216dbll-55 a minimum setup of 5ns (1 cycle) with at least 45ns
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(6 cycles) for CPU read/write and no hold time is required.
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Note: Since no hold parameter is available at SMC the atmel,smc-cycle-timing
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should have additional cycles to accommodate for hold values.
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No Hold Time:
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cycle-timing (7) = setup (1) + pulse (6) + hold (0)
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With 3 Hold Times:
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cycle-timing (10) = setup (1) + pulse (6) + hold (3)
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Finally, in order to make the memory available you will need to define new
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memory device/s in DeviceTree:
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sram1: sram@60000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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device_type = "memory";
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reg = <0x60000000 DT_SIZE_K(512)>;
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zephyr,memory-region = "SRAM1";
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};
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compatible: "atmel,sam-smc"
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include: [base.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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clocks:
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required: true
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 0
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child-binding:
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description: |
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Child device nodes are representing devices connected to the EBI/SMC bus.
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properties:
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reg:
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type: int
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required: true
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description: |
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The device's SMC Chip Select number.
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Valid range: 0 - 3
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atmel,smc-write-mode:
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type: string
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required: true
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description: |
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Select which signal is used for the write operation, either the chip
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select (ncs) or a dedicated write enable pin (nwe). The data is put
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on the bus during the pulse and hold steps of that signal.
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The internal data buffers are switched to output mode after the NCS_WR
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or NWE setup time.
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enum:
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- "ncs"
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- "nwe"
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atmel,smc-read-mode:
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type: string
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required: true
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description: |
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Select which signal is used for the read operation, either the chip
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select (ncs) or a dedicated output enable pin (nrd). The data is read
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from the bus during the pulse and hold steps of that signal.
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enum:
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- "ncs"
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- "nrd"
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atmel,smc-setup-timing:
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type: array
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required: true
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description: |
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This value is used to setup memory region (set address). The setup
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values is an array of the signals NWE, NCS_WR, NRD and NCS_RD
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where each value is configured in terms of MCK cycles. The SMC
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controller allows use of setups value of 0 (no delays) when
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consecutive reads/writes are used. Each value is encoded in
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6 bits where the highest bit adds an offset of 128 cycles.
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The effective value for each element is: 128 x setup[5] + setup[4:0]
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atmel,smc-pulse-timing:
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type: array
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required: true
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description: |
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This value is used to effectivelly read/write at memory region (pulse phase).
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The pulse value is an array of the signals NWE, NCS_WR, NRD and NCS_RD where
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each value is configured in terms of MCK cycles and a value of 0 is forbidden.
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Each value is encoded in 7 bits where the highest bit adds an offset of 256
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cycles. The effective value for each element is: 256 x setup[6] + setup[5:0]
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atmel,smc-cycle-timing:
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type: array
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required: true
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description: |
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SMC timing configurations in cycles for the total write and read
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length respectively.
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This value describes the entire write/read operation timing which
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is defined as: cycle = setup + pulse + hold
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Value has to be greater or equal to setup + pulse timing and
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is encoded in 9 bits where the two highest bits are multiplied
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with an offset of 256.
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Effective value for each element: 256 x cycle[8:7] + cycle[6:0]
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