473 lines
16 KiB
YAML
473 lines
16 KiB
YAML
# Copyright(c) 2024 Intel Corporation.
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# SPDX - License - Identifier : Apache - 2.0
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compatible: "snps,dwcxgmac"
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description: Synopsys DesignWareCore XGMAC
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include:
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- name: reset-device.yaml
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- name: ethernet-controller.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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max-frame-size:
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type: int
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default: 1518
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description: |
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Maximum ethernet frame size. The current ethernet frame sizes
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supported by hardware are standard and jumbo (up to 16KB) frames. This
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means that normally xgmac will reject any frame above max-frame-size
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value. The default value is 1518, which represents an usual
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IEEE 802.3 ethernet frame:
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Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes
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max-speed:
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type: int
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enum:
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- 10
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- 100
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- 1000
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- 2500
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default: 1000
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description: |
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This specifies maximum speed in Mbit/s supported by the device. The
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xgmac driver supports 10Mbit/s, 100Mbit/s, 1000Mbit/s, and 2500Mbit/s. Using 1000,
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as default value, enables driver to configure 10 and 100Mbit/s speeds.
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2500Mbit/s speed can be used only with Soft PCS. When selected driver assumes
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soft PCS is connected to XGMAC through GMII. make sure the phy-connection-type is
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selected as gmii when 2500Mbit/s speed is selected.
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tx-fifo-size:
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type: int
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enum:
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- 1024
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- 2048
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- 4096
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- 8192
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- 16384
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- 32768
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- 65536
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- 131072
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- 262144
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default: 32768
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description: |
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Specifies the size of the MTL Transmit FIFO
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rx-fifo-size:
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type: int
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enum:
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- 1024
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- 2048
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- 4096
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- 8192
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- 16384
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- 32768
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- 65536
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- 131072
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- 262144
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default: 32768
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description: |
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Specifies the size of the MTL Receive FIFO
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num-dma-ch:
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type: int
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required: true
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description: |
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Number of dma channels range: 1 to 8.
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num-tx-queues:
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type: int
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required: true
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description: |
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Number of hardware TX queues range: 1 to 8.
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num-rx-queues:
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type: int
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required: true
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description: |
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Number of hardware RX queues range: 1 to 8.
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num-tc:
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type: int
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default: 1
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description: |
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Number of traffic classes range: 1 to 7.
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full-duplex-mode-en:
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type: boolean
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required: true
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description: |
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MAC communication mode to full duplex mode.
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wr-osr-lmt:
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type: int
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default: 31
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description: |
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AXI Maximum Write Outstanding Request Limit.This value
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limits the maximum outstanding request on the AXI write
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interface. Maximum outstanding requests = WR_OSR_LMT + 1
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rd-osr-lmt:
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type: int
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default: 31
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description: |
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AXI Maximum Read Outstanding Request Limit.This value
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limits the maximum outstanding request on the AXI read
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interface. Maximum outstanding requests = WR_OSR_LMT + 1
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pbl:
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type: int
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default: 32
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description: |
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Programmable burst length range: 4,5,16,32,64,128,256
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edma-tdps:
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type: int
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default: 1
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description: |
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Tx Descriptor Pre-fetch threshold Size.
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This field controls the threshold in the Descriptor cache after
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which the DMA starts pre-fetching the TxDMA descriptors. The
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DMA engine for all TxDMA channels initiate requests for the
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descriptor fetches as soon as the number of descriptors in the
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cache memory for that DMA channel, falls below or equal to
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the programmed threshold (each descriptor is 16 bytes)
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Range: 0,1,2,3,4,5
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edma-rdps:
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type: int
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default: 1
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description: |
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Rx Descriptor Pre-fetch threshold Size.
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This field controls the threshold in the Descriptor cache after
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which the DMA starts pre-fetching the RxDMA descriptors. The
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DMA engine for all RxDMA channels initiate requests for the
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descriptor fetches as soon as the number of descriptors in the
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cache memory for that DMA channel, falls below or equal to
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the programmed threshold (each descriptor is 16 bytes)
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Range: 0,1,2,3,4,5
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pblx8:
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type: boolean
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description: |
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8xPBL mode.
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When this is set to true, the PBL value is multiplied eight times.
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Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256
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beats depending on the PBL value.
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ubl:
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type: boolean
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description: |
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AXI Undefined Burst Length.
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1: The AXI master can perform burst transfers that are equal to or less
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than the maximum allowed burst length enabled.
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0: The AXI master performs one of the following burst transfers: Burst
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transfers of fixed burst lengths as indicated by the BLEN256, BLEN128,
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BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4 field.
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blen4:
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type: boolean
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description: |
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AXI Burst Length 4.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 4 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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blen8:
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type: boolean
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description: |
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AXI Burst Length 8.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 8 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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blen16:
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type: boolean
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description: |
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AXI Burst Length 16.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 16 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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blen32:
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type: boolean
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description: |
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AXI Burst Length 32.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 32 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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blen64:
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type: boolean
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description: |
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AXI Burst Length 64.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 64 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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blen128:
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type: boolean
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description: |
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AXI Burst Length 128.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 128 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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blen256:
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type: boolean
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description: |
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AXI Burst Length 256.
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When this enabled and the mixed_burst is disabled, the AXI master
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can select a burst length of 256 on the AXI interface.
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When the mixed_burst enabled, enabling this field has no effect.
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aal:
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type: boolean
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description: |
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Address-Aligned Beats.
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When this is enabled, the AXI master performs address-aligned
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burst transfers on Read and Write channels.
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eame:
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type: boolean
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description: |
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Enhanced Address Mode Enable.
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DMA master enables the enhanced address mode (40-bit or 48-bit addressing mode).
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In this mode, the DMA engine uses either the 40-bit or 48-bit address, depending
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on the configuration.
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dma-ch-mss:
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type: int
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default: 4096
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description: |
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Maximum Segment Size.
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This field specifies the maximum segment size that must be
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used while segmenting the Transmit packet. This field is valid
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only if the TSE enabled.
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dma-ch-tdrl:
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type: int
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default: 512
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description: |
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Transmit Descriptor Ring Length.
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This field sets the maximum number of Tx descriptors in the
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circular descriptor ring. The maximum number of descriptors is
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limited to 16384 descriptors.
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dma-ch-rdrl:
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type: int
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default: 512
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description: |
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Receive Descriptor Ring Length.
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This field sets the maximum number of Rx descriptors in the
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circular descriptor ring. The maximum number of descriptors is
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limited to 16384 descriptors.
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dma-ch-rbsz:
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type: int
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default: 16383
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description: |
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Receive Buffer size.
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This field indicates the size of the Rx buffers specified in bytes
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allocated by the software to store the packets the Rx DMA
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transfers to the host memory. The maximum buffer size is
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limited to 16K bytes. The buffer size is applicable to payload
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buffers when split headers are enabled.
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dma-ch-arbs:
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type: int
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default: 0
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description: |
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Alternate Receive Buffer Size
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Indicates size in bytes for Buffer 1 when ARBS is set
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to a non-zero value (when split header(SPH) feature is not enabled).
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When split header feature is enabled, ARBS indicates the
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buffer size for header data. The maximum alternate buffer is
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limited to 1016 or 1008-bytes depending on the data bus
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widths (64-bit or 128-bit respectively). When ARBS=0, Rx
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Buffer1 and Rx Buffer2 sizes are based on RBSZ field. Width of
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ARBS field is 7 or 6-bits depending on the data bus widths
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(64-bit or 128-bit respectively).
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dma-ch-rxpbl:
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type: int
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default: 32
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description: |
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Receive Programmable Burst Length.
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These field indicate the maximum number of beats to be
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transferred in one DMA data transfer.
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dma-ch-txpbl:
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type: int
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default: 32
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description: |
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Transmit Programmable Burst Length.
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These field indicate the maximum number of beats to be
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transferred in one DMA data transfer.
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dma-ch-sph:
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type: boolean
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description: |
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Header-Payload Split.
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When this field is set, the DMA splits the header and payload in
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the Receive path. The DMA writes the header to the Buffer
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Address1. The DMA writes the payload to the buffer to which
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the Buffer Address2 is pointing.
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The software must ensure that the header fits into the Receive
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buffers. If the header length exceeds the receive buffer size,
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the DMA does not split the header and payload.
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dma-ch-edse:
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type: boolean
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description: |
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Enhanced Descriptor Enable.
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When this field is set, the corresponding channel uses
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enhanced Descriptors.
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dma-ch-tse:
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type: boolean
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description: |
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TCP Segmentation Enabled.
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When this field is set, the DMA performs the TCP segmentation
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for packets in Channel. The TCP segmentation is done only
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for those packets for which the TSE is set in the Tx Normal
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descriptor.
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dma-ch-osp:
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type: boolean
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description: |
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Operate on Second Packet.
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When this field is set, it instructs the DMA to process the second
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packet of the Transmit data even before closing the descriptor
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of the first packet.
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mtl-raa:
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type: boolean
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description: |
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Receive Arbitration Algorithm.
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This field is used to select the arbitration algorithm for the Rx
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side. 0: Strict Priority (SP), 1: Weighted Strict Priority (WSP)
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mtl-etsalg:
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type: int
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default: 0
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description: |
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ETS Algorithm.
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This field selects the type of ETS algorithm to be applied for
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traffic classes whose transmission selection algorithm (TSA) is
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set to ETS:
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0: WRR algorithm
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1: WFQ algorithm
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2: DWRR algorithm
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rxq-dyn-dma-en:
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type: int
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default: 1
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description: |
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Receive Queue Enabled for Dynamic DMA Channel Selection.
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Each bit position of this field maps to a queue. there are total 8 queues
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rxq-dma-ch-sel:
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type: uint8-array
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default: [0, 1, 2, 3, 4, 5, 6, 7]
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description: |
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Receive Queue Mapped to DMA Channel. this field does not have
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effect when rxQ-DynDma-En is enabled.
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range 0 - 7
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txq-size:
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type: uint8-array
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default: [127]
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description: |
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This field indicates the size of the allocated Transmit queues
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in blocks of 256 bytes. = (txQ-size + 1) x 256
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range: 0 - 7
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map-queue-tc:
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type: uint8-array
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default: [0]
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description: |
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Queue to Traffic Class Mapping. range 0 - 7
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tx-threshold-ctrl:
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type: uint8-array
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default: [0]
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description: |
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Transmit Threshold Control.
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These field control the threshold level of the MTL Tx Queue.
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Transmission starts when the packet size within the MTL Tx
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Queue is larger than the threshold. In addition, full packets
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with length less than the threshold are also transmitted. This
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field us used only when Transmit Store and Forward is disabled.
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range 0 - 7
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0: 64
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1: reserved
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2: 96
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3: 128
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4: 192
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5: 256
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6: 384
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7: 512
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rx-threshold-ctrl:
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type: uint8-array
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default: [0]
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description: |
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The received packet is transferred to the application or DMA
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when the packet size within the MTL Rx queue is larger than
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the threshold. In addition, full packets with length less than the
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threshold are automatically transferred. The value of 11 is not
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applicable if the size of the configured Rx Queue is 128 bytes.
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This field is valid only when the RSF bit is zero. This field is
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ignored when the RSF field is set to 1.
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range 0 - 3
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0: 64
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1: reserved
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2: 96
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3: 128
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rxq-size:
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type: uint8-array
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default: [127]
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description: |
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Receive Queue Size. This field indicates the size of the allocated
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Receive queues in blocks 256 bytes. = (rxQ-size + 1) x 256
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Range: 0 - 127 ,
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tx-store-fwrd-en:
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type: int
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default: 255
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description: |
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Transmit Store and Forward. When this field is set, the transmission
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starts when a full packet resides in the MTL Tx Queue.
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Each bit position of this field maps to a queue. there are total 8 queues
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hfc-en:
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type: int
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default: 0
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description: |
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Enable Hardware Flow Control. When this field is set, the flow control
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signal operation, based on the fill-level of Rx queue, is enabled.
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Each bit position of this field maps to a queue. there are total 8 queues
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cs-error-pkt-drop-dis:
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type: int
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default: 0
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description: |
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Disable Dropping of TCP/IP Checksum Error Packets
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Each bit position of this field maps to a queue. there are total 8 queues
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rx-store-fwrd-en:
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type: int
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default: 255
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description: |
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Receive Store and Forward. When this field is set, DWC_xgmac reads a
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packet from the Rx queue only after the complete packet has been written to it.
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Each bit position of this field maps to a queue. there are total 8 queues
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fep-en:
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type: int
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default: 0
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description: |
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Forward Error Packets. When this bit is set, all packets except the runt error
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packets are forwarded to the application or DMA.
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Each bit position of this field maps to a queue. there are total 8 queues
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fup-en:
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type: int
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default: 0
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description: |
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Forward Undersized Good Packets. When this field is set, the Rx queue forwards
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the undersized good packets.
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Each bit position of this field maps to a queue. there are total 8 queues
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priorities-map-tc:
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type: array
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default: [0]
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description: |
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Priorities Mapped to Traffic Class. This field determines if the transmit
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queues associated with the traffic class should be blocked from transmitting
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for the specified pause time when a PFC packet is received with priorities
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matching the priorities programmed in this field.
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range: 0 - 7 and max array size is 8
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ex: <0,1,2,3,4,5,6,7>
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tx-sel-algorithm:
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type: uint8-array
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default: [0]
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description: |
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Transmission Selection Algorithm. This field is used to assign a transmission
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selection algorithm for this traffic class.
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range: 0 -strict priority
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1 - Credit based shaper
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2 - Enhanced Transmission Selection
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jumbo-pkt-en:
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type: boolean
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description: |
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Jumbo Packet Enable.
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When this bit is set, the MAC allows jumbo packets of 9018
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bytes (9022 bytes for VLAN tagged packets) without reporting
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a giant packet error in the Rx packet status
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gaint-pkt-size-limit:
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type: int
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default: 9018
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description: |
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Giant Packet Size Limit.
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If the received packet size is greater than the value
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programmed in this field in units of bytes, the MAC declares
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the received packet as Giant packet. The value programmed in
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this field must be greater than or equal to 1518 bytes. Any
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other programmed value is considered as 1518 bytes.
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