523 lines
12 KiB
Plaintext
523 lines
12 KiB
Plaintext
/*
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* Copyright (c) 2023-2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/clock/stm32wba_clock.h>
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#include <zephyr/dt-bindings/reset/stm32wba_reset.h>
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#include <zephyr/dt-bindings/adc/stm32u5_adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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st,lptim-stdby-timer = &rtc;
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zephyr,bt-hci = &bt_hci_wba;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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/* Do not add &standby here since CONFIG_PM_S2RAM is disabled by default */
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cpu-power-states = <&stop0 &stop1>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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power-states {
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stop0: state0 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <1>;
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min-residency-us = <100>;
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};
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stop1: state1 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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substate-id = <2>;
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min-residency-us = <500>;
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};
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standby: state2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-ram";
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substate-id = <1>;
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min-residency-us = <1000>;
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exit-latency-us = <50>;
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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/* Defining this memory solves unaligned memory access issue */
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sram6: memory@48028000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x48028000 DT_SIZE_K(16)>;
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device_type = "memory";
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zephyr,memory-region = "SRAM6";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32wba-hse-clock";
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clock-frequency = <DT_FREQ_M(32)>;
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <1>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll1: pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32wba-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32wba-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <6 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <16>;
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erase-block-size = <8192>;
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/* maximum erase time(ms) for a 8K sector */
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max-erase-time = <5>;
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};
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};
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rcc: rcc@46020c00 {
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compatible = "st,stm32wba-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x46020c00 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@46022000 {
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compatible = "st,stm32g0-exti", "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x46022000 0x400>;
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num-lines = <16>;
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interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
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<15 0>, <16 0>, <17 0>, <18 0>,
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<19 0>, <20 0>, <21 0>, <22 0>,
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<23 0>, <24 0>, <25 0>, <26 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5", "line6", "line7",
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"line8", "line9", "line10", "line11",
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"line12", "line13", "line14", "line15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 1>, <6 1>, <7 1>,
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<8 1>, <9 1>, <10 1>, <11 1>,
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<12 1>, <13 1>, <14 1>, <15 1>;
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};
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2000>;
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gpioa: gpio@42020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
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};
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gpiob: gpio@42020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
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};
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gpioc: gpio@42020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
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};
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gpioh: gpio@42021c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
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};
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};
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rtc: rtc@46007800 {
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compatible = "st,stm32-rtc";
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reg = <0x46007800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00200000>;
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alarms-count = <2>;
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status = "disabled";
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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resets = <&rctl STM32_RESET(APB2, 14U)>;
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interrupts = <46 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1L, 17U)>;
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interrupts = <47 0>;
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status = "disabled";
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};
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lpuart1: serial@46002400 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x46002400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000040>;
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resets = <&rctl STM32_RESET(APB7, 6U)>;
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interrupts = <48 0>;
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <45 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "disabled";
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};
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spi3: spi@46002000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46002000 0x400>;
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interrupts = <63 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000020>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <43 0>, <44 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c3: i2c@46002800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46002800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000080>;
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interrupts = <54 0>, <55 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
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resets = <&rctl STM32_RESET(APB2, 11U)>;
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interrupts = <37 0>, <38 0>, <39 0>, <40 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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resets = <&rctl STM32_RESET(APB1L, 0U)>;
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interrupts = <41 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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resets = <&rctl STM32_RESET(APB1L, 1U)>;
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interrupts = <42 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
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resets = <&rctl STM32_RESET(APB2, 17U)>;
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interrupts = <51 0>;
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interrupt-names = "global";
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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resets = <&rctl STM32_RESET(APB2, 18U)>;
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interrupts = <52 0>;
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interrupt-names = "global";
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status = "disabled";
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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adc4: adc@46021000 {
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compatible = "st,stm32-adc";
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reg = <0x46021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>,
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<&rcc STM32_SRC_HCLK1 ADC_SEL(0)>;
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interrupts = <65 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <2 4 8 13 20 40 80 815>;
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num-sampling-time-common-channels = <2>;
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st,adc-clock-source = <ASYNC>;
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st,adc-sequencer = <NOT_FULLY_CONFIGURABLE>;
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};
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lptim1: timers@46004400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>;
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interrupts = <49 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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lptim2: timers@40009400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
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interrupts = <50 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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rng: rng@420c0800 {
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compatible = "st,stm32-rng";
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reg = <0x420c0800 0x400>;
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interrupts = <59 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
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<&rcc STM32_SRC_HSI16 RNG_SEL(2)>;
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nist-config = <0xf00d>;
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health-test-config = <0xaac7>;
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status = "disabled";
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};
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gpdma1: dma@40020000 {
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compatible = "st,stm32u5-dma";
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#dma-cells = <3>;
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reg = <0x40020000 0x1000>;
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interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
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dma-channels = <8>;
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dma-requests = <52>;
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dma-offset = <0>;
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status = "disabled";
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};
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};
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die_temp: dietemp {
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compatible = "st,stm32-temp-cal";
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ts-cal1-addr = <0x0BF90710>;
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ts-cal2-addr = <0x0BF90742>;
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ts-cal1-temp = <30>;
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ts-cal2-temp = <130>;
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ts-cal-vrefanalog = <3000>;
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io-channels = <&adc4 13>;
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status = "disabled";
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};
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bt_hci_wba: bt_hci_wba {
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compatible = "st,hci-stm32wba";
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status = "okay";
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};
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swj_port: swj_port {
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compatible = "swj-connector";
|
|
pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14
|
|
&debug_jtdi_pa15 &debug_jtdo_swo_pb3
|
|
&debug_jtrst_pb4>;
|
|
pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15
|
|
&analog_pb3 &analog_pb4>;
|
|
pinctrl-names = "default", "sleep";
|
|
};
|
|
|
|
smbus1: smbus1 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
smbus3: smbus3 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|