81 lines
1.9 KiB
Plaintext
81 lines
1.9 KiB
Plaintext
/*
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* Copyright (c) 2021 Guðni Már Gilbert
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/g4/stm32g4.dtsi>
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/ {
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soc {
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compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
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fdcan2: can@40006800 {
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compatible = "st,stm32-fdcan";
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reg = <0x40006800 0x400>, <0x4000a400 0x6a0>;
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reg-names = "m_can", "message_ram";
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interrupts = <86 0>, <87 0>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
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status = "disabled";
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};
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timers20: timers@40015000 {
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compatible = "st,stm32-timers";
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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resets = <&rctl STM32_RESET(APB2, 20U)>;
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interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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dma1: dma@40020000 {
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
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dma-requests = <8>;
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};
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dma2: dma@40020400 {
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interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
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dma-requests = <8>;
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dma-offset = <8>;
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};
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dmamux1: dmamux@40020800 {
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dma-channels = <16>;
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};
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adc3: adc@50000400 {
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compatible = "st,stm32-adc";
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reg = <0x50000400 0x100>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
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interrupts = <47 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32_ADC_RES(12, 0x00)
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STM32_ADC_RES(10, 0x01)
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STM32_ADC_RES(8, 0x02)
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STM32_ADC_RES(6, 0x03)>;
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sampling-times = <3 7 13 25 48 93 248 641>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1L, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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};
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};
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