224 lines
5.0 KiB
Plaintext
224 lines
5.0 KiB
Plaintext
/*
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* Copyright (c) 2017 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f3/stm32f3.dtsi>
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#include <zephyr/dt-bindings/adc/stm32f1_adc.h>
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/ {
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soc {
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compatible = "st,stm32f373", "st,stm32f3", "simple-bus";
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rcc: rcc@40021000 {
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/*
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* Use the STM32F1 compatible that define the same ADC
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* prescaler in the RCC register
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*/
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compatible = "st,stm32f1-rcc";
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};
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pinctrl: pin-controller@48000000 {
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
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};
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
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/* I2C clock source should always be defined,
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* even for the default value
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*/
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<&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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resets = <&rctl STM32_RESET(APB1, 2U)>;
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interrupts = <30 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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resets = <&rctl STM32_RESET(APB1, 3U)>;
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interrupts = <50 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers12: timers@40001800 {
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compatible = "st,stm32-timers";
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reg = <0x40001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
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resets = <&rctl STM32_RESET(APB1, 6U)>;
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interrupts = <43 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers13: timers@40001c00 {
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compatible = "st,stm32-timers";
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reg = <0x40001c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
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resets = <&rctl STM32_RESET(APB1, 7U)>;
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interrupts = <44 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers14: timers@40002000 {
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
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resets = <&rctl STM32_RESET(APB1, 8U)>;
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interrupts = <45 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers18: timers@40009c00 {
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compatible = "st,stm32-timers";
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reg = <0x40009c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
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resets = <&rctl STM32_RESET(APB1, 9U)>;
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interrupts = <27 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers19: timers@40015c00 {
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compatible = "st,stm32-timers";
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reg = <0x40015c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
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resets = <&rctl STM32_RESET(APB2, 19U)>;
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interrupts = <78 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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adc1: adc@40012400 {
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compatible = "st,stm32f1-adc", "st,stm32-adc";
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reg = <0x40012400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
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interrupts = <18 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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resolutions = <STM32F1_ADC_RES(12)>;
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sampling-times = <2 8 14 29 42 56 72 240>;
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st,adc-sequencer = <FULLY_CONFIGURABLE>;
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};
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rtc@40002800 {
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bbram: backup_regs {
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compatible = "st,stm32-bbram";
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st,backup-regs = <32>;
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status = "disabled";
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};
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};
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};
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vref: vref {
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io-channels = <&adc1 17>;
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};
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vbat: vbat {
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io-channels = <&adc1 18>;
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};
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smbus2: smbus2 {
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compatible = "st,stm32-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c = <&i2c2>;
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status = "disabled";
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};
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};
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