267 lines
6.6 KiB
Plaintext
267 lines
6.6 KiB
Plaintext
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* Copyright (c) 2017 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#include <devicetree.h>
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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#define RAMABLE_REGION dram0_0_seg :dram0_0_phdr
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#define ROMABLE_REGION iram0_0_seg :iram0_0_phdr
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PROVIDE ( __stack = 0x3ffe3f20 );
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PROVIDE ( esp32_rom_uart_tx_one_char = 0x40009200 );
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PROVIDE ( esp32_rom_uart_rx_one_char = 0x400092d0 );
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PROVIDE ( esp32_rom_uart_attach = 0x40008fd0 );
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PROVIDE ( esp32_rom_uart_tx_wait_idle = 0x40009278 );
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PROVIDE ( esp32_rom_intr_matrix_set = 0x4000681c );
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PROVIDE ( esp32_rom_gpio_matrix_in = 0x40009edc );
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PROVIDE ( esp32_rom_gpio_matrix_out = 0x40009f0c );
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PROVIDE ( esp32_rom_Cache_Flush = 0x40009a14 );
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PROVIDE ( esp32_rom_Cache_Read_Enable = 0x40009a84 );
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PROVIDE ( esp32_rom_ets_set_appcpu_boot_addr = 0x4000689c );
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PROVIDE ( esp32_rom_i2c_readReg = 0x40004148 );
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PROVIDE ( esp32_rom_i2c_writeReg = 0x400041a4 );
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MEMORY
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{
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iram0_0_seg(RX): org = 0x40080000, len = 0x20000
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iram0_2_seg(RX): org = 0x400D0018, len = 0x330000
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dram0_0_seg(RW): org = 0x3FFB0000, len = 0x50000
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drom0_0_seg(R): org = 0x3F400010, len = 0x800000
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rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
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rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
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#endif
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}
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PHDRS
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{
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iram0_0_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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}
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/* Default entry point: */
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PROVIDE ( _ResetVector = 0x40000400 );
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ENTRY(CONFIG_KERNEL_ENTRY)
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0x40000450);
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PROVIDE(_memmap_reset_vector = 0x40000400);
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SECTIONS
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{
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#include <linker/rel-sections.ld>
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/* RTC fast memory holds RTC wake stub code,
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including from any source file named rtc_wake_stub*.c
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*/
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.rtc.text :
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{
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. = ALIGN(4);
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*(.rtc.literal .rtc.text)
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*rtc_wake_stub*.o(.literal .text .literal.* .text.*)
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} >rtc_iram_seg
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/* RTC slow memory holds RTC wake stub
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data/rodata, including from any source file
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named rtc_wake_stub*.c
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*/
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.rtc.data :
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{
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_rtc_data_start = ABSOLUTE(.);
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*(.rtc.data)
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*(.rtc.rodata)
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*rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
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_rtc_data_end = ABSOLUTE(.);
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} > rtc_slow_seg
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/* RTC bss, from any source file named rtc_wake_stub*.c */
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.rtc.bss (NOLOAD) :
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{
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_rtc_bss_start = ABSOLUTE(.);
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*rtc_wake_stub*.o(.bss .bss.*)
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*rtc_wake_stub*.o(COMMON)
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_rtc_bss_end = ABSOLUTE(.);
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} > rtc_slow_seg
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/* Send .iram0 code to iram */
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.iram0.vectors : ALIGN(4)
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{
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/* Vectors go to IRAM */
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_init_start = ABSOLUTE(.);
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/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
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. = 0x0;
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KEEP(*(.WindowVectors.text));
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. = 0x180;
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KEEP(*(.Level2InterruptVector.text));
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. = 0x1c0;
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KEEP(*(.Level3InterruptVector.text));
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. = 0x200;
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KEEP(*(.Level4InterruptVector.text));
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. = 0x240;
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KEEP(*(.Level5InterruptVector.text));
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. = 0x280;
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KEEP(*(.DebugExceptionVector.text));
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. = 0x2c0;
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KEEP(*(.NMIExceptionVector.text));
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. = 0x300;
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KEEP(*(.KernelExceptionVector.text));
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. = 0x340;
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KEEP(*(.UserExceptionVector.text));
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. = 0x3C0;
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KEEP(*(.DoubleExceptionVector.text));
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. = 0x400;
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*(.*Vector.literal)
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*(.UserEnter.literal);
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*(.UserEnter.text);
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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_init_end = ABSOLUTE(.);
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/* This goes here, not at top of linker script, so addr2line finds it last,
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and uses it in preference to the first symbol in IRAM */
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_iram_start = ABSOLUTE(0);
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} GROUP_LINK_IN(ROMABLE_REGION)
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#include <linker/common-ram.ld>
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#include <linker/common-rom.ld>
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SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4))
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{
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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*(.iram1 .iram1.*)
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*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
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*(.literal .text .literal.* .text.*)
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_iram_text_end = ABSOLUTE(.);
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} GROUP_LINK_IN(ROMABLE_REGION)
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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KEEP(*(.jcr))
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*(.dram1 .dram1.*)
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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} GROUP_LINK_IN(RAMABLE_REGION)
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(4))
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
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KEEP (*(.xt_except_table))
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KEEP (*(.gcc_except_table .gcc_except_table.*))
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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KEEP (*(.eh_frame))
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/* C++ constructor and destructor tables, properly ordered: */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_rodata_end = ABSOLUTE(.);
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} GROUP_LINK_IN(RAMABLE_REGION)
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/* Shared RAM */
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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} GROUP_LINK_IN(RAMABLE_REGION)
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SECTION_DATA_PROLOGUE(_APP_NOINIT_SECTION_NAME, (NOLOAD),)
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{
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. = ALIGN (8);
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*(.app_noinit)
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*("app_noinit.*")
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. = ALIGN (8);
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_app_end = ABSOLUTE(.);
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} GROUP_LINK_IN(RAMABLE_REGION)
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SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),)
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{
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. = ALIGN (8);
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*(.noinit)
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*(".noinit.*")
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. = ALIGN (8);
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_heap_start = ABSOLUTE(.);
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} GROUP_LINK_IN(RAMABLE_REGION)
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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#include <linker/debug-sections.ld>
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SECTION_PROLOGUE(.xtensa.info, 0,)
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{
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*(.xtensa.info)
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}
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}
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