zephyr/soc/xtensa
Torsten Rasmussen 13153678cb xtensa: SOC_DIR usage cleanup.
This commit is a cleanup of the SOC_DIR usage.
This cleanup is a preparation for supporting a list of SOC_ROOT instead
of just allowing one SOC_ROOT.

Supporting a list of SOC_ROOTs allows for placing of SOC in Zephyr
modules. It also aligns how BOARD_ROOT supports a list, and thus usage
of n_ROOT in Zephyr becomes more consistent.

This commit introduces the following changes:
- soc/xtensa/intel_apl_adsp/bootloader.cmake removed.
  This file is not included elsewhere in the build system, and appears
  to be leftover from #25133. Almost identical content is found in
  `soc/xtensa/intel_apl_adsp/commonbootloader.cmake`
- Changed xtensa/intel_apl_adsp to named library. Using a named library
  allow fetching library files based on library name without the need to
  know build path (and thus removes the need for knowing `${SOC_DIR}`).
- Changed SOC_DIR/ARCH/SOC_FAMILY to use CMAKE_CURRENT_LIST_DIR for
  configure time commands, as CMake code is already located inside this
  path.
- Using generator expression for library files from other CMake targets.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2020-08-05 08:06:07 -04:00
..
esp32 drivers: esp32/clock_control: support UART, I2C 2020-06-16 09:00:51 -05:00
intel_apl_adsp xtensa: SOC_DIR usage cleanup. 2020-08-05 08:06:07 -04:00
intel_s1000 config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET 2020-07-09 14:02:38 -04:00
sample_controller arch: xtensa: replace DT_CPU_CLOCK_FREQUENCY with new dt macros 2020-04-22 11:38:33 -05:00