84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
/*
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* Copyright (c) 2018 Sean Nyekjaer
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ATMEL_SAMD_SOC_H_
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#define _ATMEL_SAMD_SOC_H_
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#ifndef _ASMLANGUAGE
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#define DONT_USE_CMSIS_INIT
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#include <zephyr/types.h>
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/* Add include for DTS generated information */
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#include <devicetree.h>
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#if defined(CONFIG_SOC_PART_NUMBER_SAMD20E14)
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#include <samd20e14.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E15)
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#include <samd20e15.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E16)
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#include <samd20e16.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E17)
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#include <samd20e17.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E18)
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#include <samd20e18.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G14)
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#include <samd20g14.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G15)
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#include <samd20g15.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G16)
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#include <samd20g16.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17)
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#include <samd20g17.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17U)
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#include <samd20g17u.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18)
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#include <samd20g18.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18U)
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#include <samd20g18u.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J14)
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#include <samd20j14.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J15)
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#include <samd20j15.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J16)
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#include <samd20j16.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J17)
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#include <samd20j17.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J18)
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#include <samd20j18.h>
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#else
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#error Library does not support the specified device.
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#endif
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#endif /* _ASMLANGUAGE */
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#include "../common/atmel_sam0_dt.h"
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/** Processor Clock (HCLK) Frequency */
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#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ
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/** Master Clock (MCK) Frequency */
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#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
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#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000
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#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#if defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
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#else
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#error Unsupported GCLK1 clock source.
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#endif
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#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#endif /* _ATMEL_SAMD_SOC_H_ */
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