334 lines
8.9 KiB
C
334 lines
8.9 KiB
C
/*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2020 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_pwm
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#include <errno.h>
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#include <soc.h>
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#include <drivers/pwm.h>
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#include <device.h>
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#include <kernel.h>
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#include <init.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_stm32, CONFIG_PWM_LOG_LEVEL);
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/** PWM data. */
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struct pwm_stm32_data {
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/** Timer clock (Hz). */
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uint32_t tim_clk;
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};
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/** PWM configuration. */
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struct pwm_stm32_config {
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/** Timer instance. */
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TIM_TypeDef *timer;
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/** Prescaler. */
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uint32_t prescaler;
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/** Clock configuration. */
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struct stm32_pclken pclken;
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};
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/** Series F3, F7, G0, G4, H7, L4, MP1 and WB have up to 6 channels, others up
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* to 4.
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*/
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#define TIMER_HAS_6CH \
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(defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X) || \
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defined(CONFIG_SOC_SERIES_STM32H7X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32MP1X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX))
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/** Maximum number of timer channels. */
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#if TIMER_HAS_6CH
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#define TIMER_MAX_CH 6u
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#else
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#define TIMER_MAX_CH 4u
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#endif
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/** Channel to LL mapping. */
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static const uint32_t ch2ll[TIMER_MAX_CH] = {
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LL_TIM_CHANNEL_CH1, LL_TIM_CHANNEL_CH2,
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LL_TIM_CHANNEL_CH3, LL_TIM_CHANNEL_CH4,
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#if TIMER_HAS_6CH
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LL_TIM_CHANNEL_CH5, LL_TIM_CHANNEL_CH6
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#endif
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};
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/** Channel to compare set function mapping. */
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static void (*const set_timer_compare[TIMER_MAX_CH])(TIM_TypeDef *,
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uint32_t) = {
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LL_TIM_OC_SetCompareCH1, LL_TIM_OC_SetCompareCH2,
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LL_TIM_OC_SetCompareCH3, LL_TIM_OC_SetCompareCH4,
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#if TIMER_HAS_6CH
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LL_TIM_OC_SetCompareCH5, LL_TIM_OC_SetCompareCH6
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#endif
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};
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static inline struct pwm_stm32_data *to_data(struct device *dev)
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{
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return dev->data;
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}
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static inline const struct pwm_stm32_config *to_config(struct device *dev)
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{
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return dev->config;
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}
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/**
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* Obtain LL polarity from PWM flags.
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*
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* @param flags PWM flags.
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*
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* @return LL polarity.
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*/
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static uint32_t get_polarity(pwm_flags_t flags)
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{
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if ((flags & PWM_POLARITY_MASK) == PWM_POLARITY_NORMAL) {
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return LL_TIM_OCPOLARITY_HIGH;
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}
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return LL_TIM_OCPOLARITY_LOW;
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}
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/**
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* Obtain timer clock speed.
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*
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* @param pclken Timer clock control subsystem.
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* @param tim_clk Where computed timer clock will be stored.
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*
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* @return 0 on success, error code otherwise.
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*/
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static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
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{
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int r;
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struct device *clk;
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uint32_t bus_clk, apb_psc;
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clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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r = clock_control_get_rate(clk, (clock_control_subsys_t *)pclken,
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&bus_clk);
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if (r < 0) {
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return r;
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}
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#if defined(CONFIG_SOC_SERIES_STM32H7X)
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32_D2PPRE1;
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} else {
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apb_psc = CONFIG_CLOCK_STM32_D2PPRE2;
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}
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/*
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* Depending on pre-scaler selection (TIMPRE), timer clock frequency
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* is defined as follows:
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*
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* - TIMPRE=0: If the APB prescaler (PPRE1, PPRE2) is configured to a
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* division factor of 1 then the timer clock equals to APB bus clock.
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* Otherwise the timer clock is set to twice the frequency of APB bus
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* clock.
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* - TIMPRE=1: If the APB prescaler (PPRE1, PPRE2) is configured to a
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* division factor of 1, 2 or 4, then the timer clock equals to HCLK.
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* Otherwise, the timer clock frequencies are set to four times to
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* the frequency of the APB domain.
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*/
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if (LL_RCC_GetTIMPrescaler() == LL_RCC_TIM_PRESCALER_TWICE) {
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if (apb_psc == 1u) {
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*tim_clk = bus_clk;
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} else {
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*tim_clk = bus_clk * 2u;
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}
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} else {
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if (apb_psc == 1u || apb_psc == 2u || apb_psc == 4u) {
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*tim_clk = SystemCoreClock;
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} else {
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*tim_clk = bus_clk * 4u;
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}
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}
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#else
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32_APB1_PRESCALER;
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}
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_SOC_SERIES_STM32G0X)
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else {
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apb_psc = CONFIG_CLOCK_STM32_APB2_PRESCALER;
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}
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#endif
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/*
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* If the APB prescaler equals 1, the timer clock frequencies
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* are set to the same frequency as that of the APB domain.
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* Otherwise, they are set to twice (×2) the frequency of the
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* APB domain.
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*/
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if (apb_psc == 1u) {
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*tim_clk = bus_clk;
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} else {
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*tim_clk = bus_clk * 2u;
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}
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#endif
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return 0;
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}
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static int pwm_stm32_pin_set(struct device *dev, uint32_t pwm,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_stm32_config *cfg = to_config(dev);
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uint32_t channel;
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if (pwm < 1u || pwm > TIMER_MAX_CH) {
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LOG_ERR("Invalid channel (%d)", pwm);
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return -EINVAL;
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}
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if (pulse_cycles > period_cycles) {
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LOG_ERR("Invalid combination of pulse and period cycles");
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return -EINVAL;
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}
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/*
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* Non 32-bit timers count from 0 up to the value in the ARR register
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* (16-bit). Thus period_cycles cannot be greater than UINT16_MAX + 1.
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*/
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if (!IS_TIM_32B_COUNTER_INSTANCE(cfg->timer) &&
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(period_cycles > UINT16_MAX + 1)) {
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return -ENOTSUP;
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}
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channel = ch2ll[pwm - 1u];
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if (period_cycles == 0u) {
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LL_TIM_CC_DisableChannel(cfg->timer, channel);
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return 0;
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}
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if (!LL_TIM_CC_IsEnabledChannel(cfg->timer, channel)) {
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LL_TIM_OC_InitTypeDef oc_init;
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LL_TIM_OC_StructInit(&oc_init);
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oc_init.OCMode = LL_TIM_OCMODE_PWM1;
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oc_init.OCState = LL_TIM_OCSTATE_ENABLE;
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oc_init.CompareValue = pulse_cycles;
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oc_init.OCPolarity = get_polarity(flags);
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oc_init.OCIdleState = LL_TIM_OCIDLESTATE_LOW;
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if (LL_TIM_OC_Init(cfg->timer, channel, &oc_init) != SUCCESS) {
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LOG_ERR("Could not initialize timer channel output");
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return -EIO;
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}
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LL_TIM_OC_EnablePreload(cfg->timer, channel);
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} else {
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LL_TIM_OC_SetPolarity(cfg->timer, channel, get_polarity(flags));
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set_timer_compare[pwm - 1u](cfg->timer, pulse_cycles);
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}
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LL_TIM_SetAutoReload(cfg->timer, period_cycles - 1u);
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return 0;
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}
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static int pwm_stm32_get_cycles_per_sec(struct device *dev, uint32_t pwm,
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uint64_t *cycles)
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{
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struct pwm_stm32_data *data = to_data(dev);
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const struct pwm_stm32_config *cfg = to_config(dev);
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*cycles = (uint64_t)(data->tim_clk / (cfg->prescaler + 1));
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return 0;
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}
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static const struct pwm_driver_api pwm_stm32_driver_api = {
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.pin_set = pwm_stm32_pin_set,
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.get_cycles_per_sec = pwm_stm32_get_cycles_per_sec,
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};
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static int pwm_stm32_init(struct device *dev)
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{
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struct pwm_stm32_data *data = to_data(dev);
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const struct pwm_stm32_config *cfg = to_config(dev);
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int r;
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struct device *clk;
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LL_TIM_InitTypeDef init;
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/* enable clock and store its speed */
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clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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r = clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken);
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if (r < 0) {
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LOG_ERR("Could not initialize clock (%d)", r);
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return r;
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}
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r = get_tim_clk(&cfg->pclken, &data->tim_clk);
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if (r < 0) {
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LOG_ERR("Could not obtain timer clock (%d)", r);
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return r;
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}
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/* initialize timer */
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LL_TIM_StructInit(&init);
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init.Prescaler = cfg->prescaler;
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init.CounterMode = LL_TIM_COUNTERMODE_UP;
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init.Autoreload = 0u;
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init.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
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init.RepetitionCounter = 0u;
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if (LL_TIM_Init(cfg->timer, &init) != SUCCESS) {
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LOG_ERR("Could not initialize timer");
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return -EIO;
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}
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/* enable outputs and counter */
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if (IS_TIM_BREAK_INSTANCE(cfg->timer)) {
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LL_TIM_EnableAllOutputs(cfg->timer);
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}
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LL_TIM_EnableCounter(cfg->timer);
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return 0;
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}
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#define DT_INST_CLK(index, inst) \
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{ \
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.bus = DT_CLOCKS_CELL(DT_INST(index, st_stm32_timers), bus), \
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.enr = DT_CLOCKS_CELL(DT_INST(index, st_stm32_timers), bits) \
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}
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#define PWM_DEVICE_INIT(index) \
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static struct pwm_stm32_data pwm_stm32_data_##index; \
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\
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static const struct pwm_stm32_config pwm_stm32_config_##index = { \
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.timer = (TIM_TypeDef *)DT_REG_ADDR( \
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DT_INST(index, st_stm32_timers)), \
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.prescaler = DT_INST_PROP(index, st_prescaler), \
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.pclken = DT_INST_CLK(index, timer) \
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}; \
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\
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DEVICE_AND_API_INIT(pwm_stm32_##index, DT_INST_LABEL(index), \
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&pwm_stm32_init, &pwm_stm32_data_##index, \
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&pwm_stm32_config_##index, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&pwm_stm32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT)
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