176 lines
4.6 KiB
C
176 lines
4.6 KiB
C
/*
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* Copyright (c) 2016 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Driver to provide the GPIO API for a simple 32-bit i/o register
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*
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* This is a driver for accessing a simple, fixed purpose, 32-bit
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* memory-mapped i/o register using the same APIs as GPIO drivers. This is
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* useful when an SoC or board has registers that aren't part of a GPIO IP
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* block and these registers are used to control things that Zephyr normally
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* expects to be specified using a GPIO pin, e.g. for driving an LED, or
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* chip-select line for an SPI device.
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*
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* The implementation expects that all bits of the hardware register are both
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* readable and writable, and that for any bits that act as outputs, the value
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* read will have the value that was last written to it. This requirement
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* stems from the use of a read-modify-write method for all changes.
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*
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* It is possible to specify a restricted mask of bits that are valid for
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* access, and whenever the register is written, the value of bits outside this
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* mask will be preserved, even when the whole port is written to using
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* gpio_port_write.
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*/
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#include <drivers/gpio/gpio_mmio32.h>
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#include <errno.h>
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static int gpio_mmio32_config(struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = context->config;
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if ((config->mask & (1 << pin)) == 0) {
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return -EINVAL; /* Pin not in our validity mask */
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}
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if (flags & ~(GPIO_INPUT | GPIO_OUTPUT |
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GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH |
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GPIO_ACTIVE_LOW)) {
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/* We ignore direction and fake polarity, rest is unsupported */
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return -ENOTSUP;
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}
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if ((flags & GPIO_OUTPUT) != 0) {
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unsigned int key;
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volatile uint32_t *reg = config->reg;
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key = irq_lock();
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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*reg = (*reg | (1 << pin));
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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*reg = (*reg & (config->mask & ~(1 << pin)));
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}
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irq_unlock(key);
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}
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return 0;
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}
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static int gpio_mmio32_port_get_raw(struct device *dev, uint32_t *value)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = context->config;
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*value = *config->reg & config->mask;
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return 0;
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}
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static int gpio_mmio32_port_set_masked_raw(struct device *dev, uint32_t mask,
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uint32_t value)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = context->config;
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volatile uint32_t *reg = config->reg;
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unsigned int key;
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mask &= config->mask;
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value &= mask;
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/* Update pin state atomically */
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key = irq_lock();
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*reg = (*reg & ~mask) | value;
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irq_unlock(key);
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return 0;
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}
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static int gpio_mmio32_port_set_bits_raw(struct device *dev, uint32_t mask)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = context->config;
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volatile uint32_t *reg = config->reg;
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unsigned int key;
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mask &= config->mask;
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/* Update pin state atomically */
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key = irq_lock();
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*reg = (*reg | mask);
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irq_unlock(key);
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return 0;
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}
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static int gpio_mmio32_port_clear_bits_raw(struct device *dev, uint32_t mask)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = context->config;
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volatile uint32_t *reg = config->reg;
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unsigned int key;
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mask &= config->mask;
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/* Update pin state atomically */
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key = irq_lock();
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*reg = (*reg & ~mask);
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irq_unlock(key);
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return 0;
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}
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static int gpio_mmio32_port_toggle_bits(struct device *dev, uint32_t mask)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = context->config;
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volatile uint32_t *reg = config->reg;
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unsigned int key;
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mask &= config->mask;
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/* Update pin state atomically */
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key = irq_lock();
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*reg = (*reg ^ mask);
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irq_unlock(key);
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return 0;
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}
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static int gpio_mmio32_pin_interrupt_configure(struct device *dev,
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gpio_pin_t pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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if (mode != GPIO_INT_MODE_DISABLED) {
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return -ENOTSUP;
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}
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return 0;
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}
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static const struct gpio_driver_api gpio_mmio32_api = {
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.pin_configure = gpio_mmio32_config,
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.port_get_raw = gpio_mmio32_port_get_raw,
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.port_set_masked_raw = gpio_mmio32_port_set_masked_raw,
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.port_set_bits_raw = gpio_mmio32_port_set_bits_raw,
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.port_clear_bits_raw = gpio_mmio32_port_clear_bits_raw,
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.port_toggle_bits = gpio_mmio32_port_toggle_bits,
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.pin_interrupt_configure = gpio_mmio32_pin_interrupt_configure,
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};
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int gpio_mmio32_init(struct device *dev)
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{
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struct gpio_mmio32_context *context = dev->data;
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const struct gpio_mmio32_config *config = dev->config;
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context->config = config;
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dev->api = &gpio_mmio32_api;
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return 0;
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}
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