371 lines
9.4 KiB
Plaintext
371 lines
9.4 KiB
Plaintext
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* Linker script for the Xtensa platform.
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*/
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#include <xtensa/config/core-isa.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#define RAMABLE_REGION RAM :sram0_phdr
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#define ROMABLE_REGION RAM :sram0_phdr
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#ifdef CONFIG_MMU
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#define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE);
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#define HDR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE)
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#define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE)
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#define LAST_RAM_ALIGN MMU_PAGE_ALIGN
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#else
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#define MMU_PAGE_ALIGN . = ALIGN(4);
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#define HDR_MMU_PAGE_ALIGN ALIGN(4)
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#define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(4096)
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#endif
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#define PHYS_SRAM0_ADDR (DT_REG_ADDR(DT_NODELABEL(sram0)))
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#define PHYS_SRAM0_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
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#define PHYS_ROM0_ADDR (DT_REG_ADDR(DT_NODELABEL(rom0)))
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#define PHYS_ROM0_SIZE (DT_REG_SIZE(DT_NODELABEL(rom0)))
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/* Usable RAM is after the exception vectors and page-aligned. */
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#define PHYS_RAM_ADDR (PHYS_SRAM0_ADDR + CONFIG_SRAM_OFFSET)
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#define PHYS_RAM_SIZE (PHYS_SRAM0_SIZE - CONFIG_SRAM_OFFSET)
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MEMORY
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{
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vectors : org = 0x00002000, len = 0x2400
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#ifdef CONFIG_XTENSA_MMU
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vec_helpers : org = 0x00002400, len = (PHYS_RAM_ADDR - 0x00002400)
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#endif
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RAM : org = PHYS_RAM_ADDR, len = PHYS_RAM_SIZE
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/* Although ROM is of size 0x02000000, we limit it to 8KB so
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* fewer L2 page table entries are needed.
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*/
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rom0_seg : org = PHYS_ROM0_ADDR, len = PHYS_ROM0_SIZE
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#ifdef CONFIG_GEN_ISR_TABLES
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/* The space before exception vectors is not being used.
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* So we stuff the temporary IDT_LIST there to avoid
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* some linker issues which would balloon the size of
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* the intermediate files (like zephyr_pre0.elf, to
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* couple hundred MBs or even GBs).
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*/
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IDT_LIST : org = 0x00000000, len = 0x2000
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#endif
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}
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PHDRS
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{
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vectors_phdr PT_LOAD;
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#ifdef CONFIG_XTENSA_MMU
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vec_helpers_phdr PT_LOAD;
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#endif
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rom0_phdr PT_LOAD;
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sram0_phdr PT_LOAD;
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sram0_bss_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(CONFIG_KERNEL_ENTRY)
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_rom_store_table = 0;
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PROVIDE(_memmap_vecbase_reset = 0x00002000);
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PROVIDE(_memmap_reset_vector = 0xFE000000);
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/* Various memory-map dependent cache attribute settings:
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*
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* Note that there is no cacheattr register which means thah
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* cacheattr is emulated through TLB way 6 (8x 512MB regions).
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* So the attributes here are the MMU memory attributes:
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* 0x3 - rwx, bypass cache
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* 0x7 - rwx, cache write back
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* 0xB - wrx, cache write through
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* Refer to the ISA manual for other attributes.
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*/
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_memmap_cacheattr_wb_base = 0x70000007;
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_memmap_cacheattr_wt_base = 0xB000000B;
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_memmap_cacheattr_bp_base = 0x30000003;
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_memmap_cacheattr_unused_mask = 0x0FFFFFF0;
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_memmap_cacheattr_wb_strict = 0x7FFFFFF7;
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_memmap_cacheattr_wt_strict = 0xBFFFFFFB;
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_memmap_cacheattr_bp_strict = 0x3FFFFFF3;
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_memmap_cacheattr_wb_allvalid = 0x73333337;
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_memmap_cacheattr_wt_allvalid = 0xB333333B;
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_memmap_cacheattr_bp_allvalid = 0x33333333;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_allvalid);
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SECTIONS
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{
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#include <zephyr/linker/rel-sections.ld>
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#ifdef CONFIG_LLEXT
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#include <zephyr/linker/llext-sections.ld>
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#endif
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <zephyr/linker/intlist.ld>
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#endif
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/* Auto-generated vector linkage, to "vectors" memory region */
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#include <xtensa_vectors.ld>
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>vectors :vectors_phdr
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#define LIB_OBJ_FUNC_IN_SECT(library, obj_file, func) \
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*##library##:##obj_file##(.literal.##func .text.##func) \
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#ifdef CONFIG_XTENSA_MMU
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.vec_helpers :
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{
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/* There is quite some space between .DoubleExceptionVector
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* and the beginning of .text. We can put exception handling
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* code here to avoid TLB misses, thus speed up exception
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* handling a little bit.
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*
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* Note: DO NOT PUT MMU init code here as this will be
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* mapped in TLB manually. This manual entry will
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* conflict with auto-refill TLB resulting in
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* TLB multi-hit exception.
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*/
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*libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.literal .text)
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*libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.iram.text .iram0.text)
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*libarch__xtensa__core.a:window_vectors.S.obj(.iram.text)
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*libarch__xtensa__core.a:crt1.S.obj(.literal .text)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_asm2.c.obj,*)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,fatal.c.obj,*)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,cpu_idle.c.obj,*)
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*(.text.arch_is_in_isr)
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/* To support backtracing */
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,xtensa_backtrace.c.obj,*)
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*libarch__xtensa__core.a:debug_helpers_asm.S.obj(.iram1.literal .iram1)
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/* Userspace related stuff */
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,userspace.S.obj,xtensa_do_syscall)
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LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,ptables.c.obj,xtensa_swap_update_page_tables)
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/* Below are to speed up execution by avoiding TLB misses
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* on frequently used functions.
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*
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* There is almost 1MB space (due to TLB pinning) so we can
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* be generous.
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*/
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LIB_OBJ_FUNC_IN_SECT(libkernel.a,,*)
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LIB_OBJ_FUNC_IN_SECT(libdrivers__console.a,,*)
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LIB_OBJ_FUNC_IN_SECT(libdrivers__timer.a,,*)
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*(.literal.z_vrfy_* .text.z_vrfy_*)
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*(.literal.z_mrsh_* .text.z_mrsh_*)
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*(.literal.z_impl_* .text.z_impl_*)
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*(.literal.z_obj_* .text.z_obj_*)
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*(.literal.k_sys_fatal_error_handler .text.k_sys_fatal_error_handler)
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} >vec_helpers :vec_helpers_phdr
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#endif /* CONFIG_XTENSA_MMU */
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#ifdef CONFIG_CODE_DATA_RELOCATION
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#include <linker_relocate.ld>
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#endif
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.ResetVector.text : ALIGN(4)
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{
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__rom_region_start = ABSOLUTE(.);
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_ResetVector_text_start = ABSOLUTE(.);
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KEEP (*(.ResetVector.text))
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_ResetVector_text_end = ABSOLUTE(.);
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} >rom0_seg :rom0_phdr
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.text : HDR_MMU_PAGE_ALIGN
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{
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_stext = .;
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__text_region_start = .;
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z_mapped_start = .;
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_text_start = ABSOLUTE(.);
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*(.entry.text)
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*(.init.literal)
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*(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
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*(.iram1.literal .iram1)
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KEEP(*(.init))
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.fini.literal)
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KEEP(*(.fini))
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*(.gnu.version)
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#include <zephyr/linker/kobject-text.ld>
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MMU_PAGE_ALIGN
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >RAMABLE_REGION
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__text_region_end = .;
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.rodata : HDR_MMU_PAGE_ALIGN
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{
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__rodata_region_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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. = ALIGN(4);
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#include <snippets-rodata.ld>
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#include <zephyr/linker/kobject-rom.ld>
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} >RAMABLE_REGION
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#include <zephyr/linker/common-rom.ld>
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#include <zephyr/linker/thread-local-storage.ld>
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#include <zephyr/linker/cplusplus-rom.ld>
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.rodata_end : ALIGN(4)
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{
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_bss_table_start = ABSOLUTE(.);
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LONG(_bss_start)
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LONG(_bss_end)
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_bss_table_end = ABSOLUTE(.);
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MMU_PAGE_ALIGN
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__rodata_region_end = ABSOLUTE(.);
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} >RAMABLE_REGION
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#ifdef CONFIG_USERSPACE
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#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN
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#define APP_SHARED_ALIGN MMU_PAGE_ALIGN
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#include <app_smem.ld>
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_image_ram_start = _app_smem_start;
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_app_smem_size = _app_smem_end - _app_smem_start;
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_app_smem_num_words = _app_smem_size >> 2;
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_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
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_app_smem_num_words = _app_smem_size >> 2;
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#endif /* CONFIG_USERSPACE */
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.data : HDR_MMU_PAGE_ALIGN
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{
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#ifndef CONFIG_USERSPACE
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_image_ram_start = ABSOLUTE(.);
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#endif
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__data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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KEEP(*(.gnu.linkonce.d.*personality*))
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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KEEP(*(.jcr))
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. = ALIGN(4);
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#include <snippets-rwdata.ld>
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. = ALIGN(4);
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MMU_PAGE_ALIGN
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__data_end = ABSOLUTE(.);
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} >RAMABLE_REGION
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#include <snippets-sections.ld>
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#include <snippets-data-sections.ld>
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#include <zephyr/linker/common-ram.ld>
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#include <zephyr/linker/cplusplus-ram.ld>
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#include <snippets-ram-sections.ld>
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.bss (NOLOAD) : HDR_MMU_PAGE_ALIGN
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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*(.sram.bss)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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MMU_PAGE_ALIGN
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} >RAM :sram0_bss_phdr
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#include <zephyr/linker/common-noinit.ld>
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/* Must be last in RAM */
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#include <zephyr/linker/kobject-data.ld>
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#include <zephyr/linker/ram-end.ld>
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_heap_start = .;
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PROVIDE(_heap_sentry = ORIGIN(RAM) + LENGTH(RAM));
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PROVIDE(_heap_end = ORIGIN(RAM) + LENGTH(RAM));
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PROVIDE(__stack = z_interrupt_stacks + CONFIG_ISR_STACK_SIZE);
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#include <zephyr/linker/debug-sections.ld>
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.xtensa.info 0 : { *(.xtensa.info) }
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.xt.insn 0 :
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{
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KEEP (*(.xt.insn))
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KEEP (*(.gnu.linkonce.x.*))
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}
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.xt.prop 0 :
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{
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KEEP (*(.xt.prop))
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KEEP (*(.xt.prop.*))
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KEEP (*(.gnu.linkonce.prop.*))
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}
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.xt.lit 0 :
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{
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KEEP (*(.xt.lit))
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KEEP (*(.xt.lit.*))
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KEEP (*(.gnu.linkonce.p.*))
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}
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.debug.xt.callgraph 0 :
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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}
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