619 lines
17 KiB
C
619 lines
17 KiB
C
/*
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* Copyright 2021,2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_mx25um51345g
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#include <zephyr/drivers/flash.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/util.h>
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#include "spi_nor.h"
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#include "memc_mcux_flexspi.h"
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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#define NOR_ERASE_VALUE 0xff
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
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#endif
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/*
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* NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
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* called while interacting with the flexspi MUST be relocated to SRAM or ITCM
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* at runtime, so that the chip does not access the flexspi to read program
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* instructions while it is being written to
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*
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* Additionally, no data used by this driver should be stored in flash.
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*/
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#if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
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#warning "Enabling flash driver logging and XIP mode simultaneously can cause \
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read-while-write hazards. This configuration is not recommended."
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#endif
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/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable) , (02 = DTR OPI Enable) */
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#if CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR
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#define NOR_FLASH_ENABLE_OCTAL_CMD 0x2
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/* In OPI DTR mode, all writes must be 2 byte aligned, and multiples of 2 bytes */
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#define NOR_WRITE_SIZE 2
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#else
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#define NOR_FLASH_ENABLE_OCTAL_CMD 0x1
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#define NOR_WRITE_SIZE 1
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#endif
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LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
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enum {
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/* Instructions matching with XIP layout */
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READ,
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WRITE_ENABLE_OPI,
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WRITE_ENABLE,
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ERASE_SECTOR,
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PAGE_PROGRAM_INPUT,
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PAGE_PROGRAM,
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READ_ID_OPI,
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ENTER_OPI,
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READ_STATUS_REG,
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ERASE_CHIP,
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};
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/* Device variables used in critical sections should be in this structure */
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struct flash_flexspi_nor_data {
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const struct device *controller;
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flexspi_device_config_t config;
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flexspi_port_t port;
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struct flash_pages_layout layout;
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struct flash_parameters flash_parameters;
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};
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static const uint32_t flash_flexspi_nor_lut[][4] = {
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[READ_ID_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[WRITE_ENABLE] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[ENTER_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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#if (NOR_FLASH_ENABLE_OCTAL_CMD == 0x1)
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[READ_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x05,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFA),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x14),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[WRITE_ENABLE_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x06,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xF9),
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},
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[ERASE_SECTOR] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x21,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xDE),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
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},
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[ERASE_CHIP] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x60,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x9F),
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},
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[READ] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xEC,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x13),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x14),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[PAGE_PROGRAM] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x12,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xED),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_8PAD, 0x04),
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},
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#else
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[READ_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xFA),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x4),
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},
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[WRITE_ENABLE_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x06,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xF9),
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},
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[ERASE_SECTOR] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x21,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xDE),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
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},
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[ERASE_CHIP] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x9F),
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},
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[READ] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xEE,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x11),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x08),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[PAGE_PROGRAM] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x12,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xED),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x04),
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},
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#endif
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};
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static int flash_flexspi_nor_get_vendor_id(const struct device *dev,
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uint8_t *vendor_id)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = data->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_ID_OPI,
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.data = &buffer,
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.dataSize = 1,
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};
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LOG_DBG("Reading id");
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ret = memc_flexspi_transfer(data->controller, &transfer);
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*vendor_id = buffer;
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return ret;
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}
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static int flash_flexspi_nor_read_status(const struct device *dev,
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uint32_t *status)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = data->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_STATUS_REG,
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.data = status,
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.dataSize = 1,
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};
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LOG_DBG("Reading status register");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_write_status(const struct device *dev,
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uint32_t *status)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = data->port,
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.cmdType = kFLEXSPI_Write,
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.SeqNumber = 1,
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.seqIndex = ENTER_OPI,
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.data = status,
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.dataSize = 1,
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};
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LOG_DBG("Writing status register");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_write_enable(const struct device *dev,
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bool enableOctal)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer;
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transfer.deviceAddress = 0;
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transfer.port = data->port;
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transfer.cmdType = kFLEXSPI_Command;
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transfer.SeqNumber = 1;
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if (enableOctal) {
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transfer.seqIndex = WRITE_ENABLE_OPI;
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} else {
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transfer.seqIndex = WRITE_ENABLE;
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}
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transfer.data = NULL;
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transfer.dataSize = 0;
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LOG_DBG("Enabling write");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_erase_sector(const struct device *dev,
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off_t offset)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = offset,
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.port = data->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = ERASE_SECTOR,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Erasing sector at 0x%08zx", (ssize_t) offset);
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_erase_chip(const struct device *dev)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = data->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = ERASE_CHIP,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Erasing chip");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_page_program(const struct device *dev,
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off_t offset, const void *buffer, size_t len)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = offset,
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.port = data->port,
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.cmdType = kFLEXSPI_Write,
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.SeqNumber = 1,
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.seqIndex = PAGE_PROGRAM,
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.data = (uint32_t *) buffer,
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.dataSize = len,
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};
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LOG_DBG("Page programming %d bytes to 0x%08zx", len, (ssize_t) offset);
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_wait_bus_busy(const struct device *dev)
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{
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uint32_t status = 0;
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int ret;
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do {
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ret = flash_flexspi_nor_read_status(dev, &status);
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LOG_DBG("status: 0x%x", status);
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if (ret) {
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LOG_ERR("Could not read status");
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return ret;
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}
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} while (status & BIT(0));
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return 0;
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}
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static int flash_flexspi_enable_octal_mode(const struct device *dev)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable, 02 = DTR OPI Enable) */
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uint32_t status = NOR_FLASH_ENABLE_OCTAL_CMD;
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flash_flexspi_nor_write_enable(dev, false);
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flash_flexspi_nor_write_status(dev, &status);
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
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return 0;
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}
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static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
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void *buffer, size_t len)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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uint8_t *src = memc_flexspi_get_ahb_address(data->controller,
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data->port,
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offset);
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memcpy(buffer, src, len);
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return 0;
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}
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static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
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const void *buffer, size_t len)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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size_t size = len;
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uint8_t *src = (uint8_t *) buffer;
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int i;
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unsigned int key = 0;
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uint8_t *dst = memc_flexspi_get_ahb_address(data->controller,
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data->port,
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offset);
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if (memc_flexspi_is_running_xip(data->controller)) {
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/*
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* ==== ENTER CRITICAL SECTION ====
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* No flash access should be performed in critical section. All
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* code and data accessed must reside in ram.
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*/
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key = irq_lock();
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}
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if (IS_ENABLED(CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR)) {
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/* Check that write size and length are even */
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if ((offset & 0x1) || (len & 0x1)) {
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return -EINVAL;
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}
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}
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while (len) {
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/* If the offset isn't a multiple of the NOR page size, we first need
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* to write the remaining part that fits, otherwise the write could
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* be wrapped around within the same page
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*/
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i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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memcpy(nor_write_buf, src, i);
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#endif
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flash_flexspi_nor_write_enable(dev, true);
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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flash_flexspi_nor_page_program(dev, offset, nor_write_buf, i);
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#else
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flash_flexspi_nor_page_program(dev, offset, src, i);
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#endif
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
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src += i;
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offset += i;
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len -= i;
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}
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if (memc_flexspi_is_running_xip(data->controller)) {
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/* ==== EXIT CRITICAL SECTION ==== */
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irq_unlock(key);
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}
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t) dst, size);
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#endif
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return 0;
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}
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static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
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size_t size)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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int num_sectors = size / SPI_NOR_SECTOR_SIZE;
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int i;
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unsigned int key = 0;
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uint8_t *dst = memc_flexspi_get_ahb_address(data->controller,
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data->port,
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offset);
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if (offset % SPI_NOR_SECTOR_SIZE) {
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LOG_ERR("Invalid offset");
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return -EINVAL;
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}
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if (size % SPI_NOR_SECTOR_SIZE) {
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LOG_ERR("Invalid size");
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return -EINVAL;
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}
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if (memc_flexspi_is_running_xip(data->controller)) {
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/*
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* ==== ENTER CRITICAL SECTION ====
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* No flash access should be performed in critical section. All
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* code and data accessed must reside in ram.
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*/
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key = irq_lock();
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}
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if ((offset == 0) && (size == data->config.flashSize * KB(1))) {
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flash_flexspi_nor_write_enable(dev, true);
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flash_flexspi_nor_erase_chip(dev);
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
|
|
} else {
|
|
for (i = 0; i < num_sectors; i++) {
|
|
flash_flexspi_nor_write_enable(dev, true);
|
|
flash_flexspi_nor_erase_sector(dev, offset);
|
|
flash_flexspi_nor_wait_bus_busy(dev);
|
|
memc_flexspi_reset(data->controller);
|
|
offset += SPI_NOR_SECTOR_SIZE;
|
|
}
|
|
}
|
|
|
|
if (memc_flexspi_is_running_xip(data->controller)) {
|
|
/* ==== EXIT CRITICAL SECTION ==== */
|
|
irq_unlock(key);
|
|
}
|
|
|
|
#ifdef CONFIG_HAS_MCUX_CACHE
|
|
DCACHE_InvalidateByRange((uint32_t) dst, size);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct flash_parameters *flash_flexspi_nor_get_parameters(
|
|
const struct device *dev)
|
|
{
|
|
struct flash_flexspi_nor_data *data = dev->data;
|
|
|
|
return &data->flash_parameters;
|
|
}
|
|
|
|
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
|
|
static void flash_flexspi_nor_pages_layout(const struct device *dev,
|
|
const struct flash_pages_layout **layout, size_t *layout_size)
|
|
{
|
|
struct flash_flexspi_nor_data *data = dev->data;
|
|
|
|
*layout = &data->layout;
|
|
*layout_size = 1;
|
|
}
|
|
#endif /* CONFIG_FLASH_PAGE_LAYOUT */
|
|
|
|
static int flash_flexspi_nor_init(const struct device *dev)
|
|
{
|
|
struct flash_flexspi_nor_data *data = dev->data;
|
|
uint8_t vendor_id;
|
|
|
|
if (!device_is_ready(data->controller)) {
|
|
LOG_ERR("Controller device not ready");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (memc_flexspi_is_running_xip(data->controller)) {
|
|
/* Wait for bus idle before configuring */
|
|
memc_flexspi_wait_bus_idle(data->controller);
|
|
}
|
|
|
|
if (memc_flexspi_set_device_config(data->controller, &data->config,
|
|
(const uint32_t *)flash_flexspi_nor_lut,
|
|
sizeof(flash_flexspi_nor_lut) / MEMC_FLEXSPI_CMD_SIZE,
|
|
data->port)) {
|
|
LOG_ERR("Could not set device configuration");
|
|
return -EINVAL;
|
|
}
|
|
|
|
memc_flexspi_reset(data->controller);
|
|
|
|
if (flash_flexspi_enable_octal_mode(dev)) {
|
|
LOG_ERR("Could not enable octal mode");
|
|
return -EIO;
|
|
}
|
|
|
|
if (flash_flexspi_nor_get_vendor_id(dev, &vendor_id)) {
|
|
LOG_ERR("Could not read vendor id");
|
|
return -EIO;
|
|
}
|
|
LOG_DBG("Vendor id: 0x%0x", vendor_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct flash_driver_api flash_flexspi_nor_api = {
|
|
.erase = flash_flexspi_nor_erase,
|
|
.write = flash_flexspi_nor_write,
|
|
.read = flash_flexspi_nor_read,
|
|
.get_parameters = flash_flexspi_nor_get_parameters,
|
|
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
|
|
.page_layout = flash_flexspi_nor_pages_layout,
|
|
#endif
|
|
};
|
|
|
|
#define CONCAT3(x, y, z) x ## y ## z
|
|
|
|
#define CS_INTERVAL_UNIT(unit) \
|
|
CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
|
|
|
|
#define AHB_WRITE_WAIT_UNIT(unit) \
|
|
CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
|
|
|
|
#define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
|
|
{ \
|
|
.flexspiRootClk = MHZ(120), \
|
|
.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
|
|
.CSIntervalUnit = \
|
|
CS_INTERVAL_UNIT( \
|
|
DT_INST_PROP(n, cs_interval_unit)), \
|
|
.CSInterval = DT_INST_PROP(n, cs_interval), \
|
|
.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
|
|
.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
|
|
.dataValidTime = DT_INST_PROP(n, data_valid_time), \
|
|
.columnspace = DT_INST_PROP(n, column_space), \
|
|
.enableWordAddress = DT_INST_PROP(n, word_addressable), \
|
|
.AWRSeqIndex = 0, \
|
|
.AWRSeqNumber = 0, \
|
|
.ARDSeqIndex = READ, \
|
|
.ARDSeqNumber = 1, \
|
|
.AHBWriteWaitUnit = \
|
|
AHB_WRITE_WAIT_UNIT( \
|
|
DT_INST_PROP(n, ahb_write_wait_unit)), \
|
|
.AHBWriteWaitInterval = \
|
|
DT_INST_PROP(n, ahb_write_wait_interval), \
|
|
} \
|
|
|
|
#define FLASH_FLEXSPI_NOR(n) \
|
|
static struct flash_flexspi_nor_data \
|
|
flash_flexspi_nor_data_##n = { \
|
|
.controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
|
|
.config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
|
|
.port = DT_INST_REG_ADDR(n), \
|
|
.layout = { \
|
|
.pages_count = DT_INST_PROP(n, size) / 8 \
|
|
/ SPI_NOR_SECTOR_SIZE, \
|
|
.pages_size = SPI_NOR_SECTOR_SIZE, \
|
|
}, \
|
|
.flash_parameters = { \
|
|
.write_block_size = NOR_WRITE_SIZE, \
|
|
.erase_value = NOR_ERASE_VALUE, \
|
|
}, \
|
|
}; \
|
|
\
|
|
DEVICE_DT_INST_DEFINE(n, \
|
|
flash_flexspi_nor_init, \
|
|
NULL, \
|
|
&flash_flexspi_nor_data_##n, \
|
|
NULL, \
|
|
POST_KERNEL, \
|
|
CONFIG_FLASH_INIT_PRIORITY, \
|
|
&flash_flexspi_nor_api);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
|