Carlo Caione 34e0294652 arm: aarch32: Use proper sys functions for cache mainteinance ... This patchset is fixing two things: 1. The proper sys_* functions are used for cache mainteinance operations. 2. To check the status of the L1 cache the SCB registers are probed so the code is assuming a core architecture cache is present, thus make the code conditionally compiled on CONFIG_ARCH_CACHE. Signed-off-by: Carlo Caione <ccaione@baylibre.com>		2023-01-10 18:22:32 -05:00
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cortex_a_r	arch: aarch32: add caches capability to Cortex-R52	2022-12-12 10:39:31 +01:00
cortex_m	arm: aarch32: Use proper sys functions for cache mainteinance	2023-01-10 18:22:32 -05:00
mmu	…
mpu	arm: aarch32: config static regions with MPU disabled	2022-12-12 10:39:31 +01:00
CMakeLists.txt	cache: Rework cache API	2022-12-01 13:40:56 -05:00
Kconfig	arch: support nocache for Cortex-R52	2022-12-12 10:39:31 +01:00
Kconfig.vfp	…
__aeabi_atexit.c	…
cache.c	arm: cache: Rework cache API	2022-12-01 13:40:56 -05:00
cpu_idle.S	…
fatal.c	…
irq_manage.c	…
irq_offload.c	…
irq_relay.S	…
isr_wrapper.S	…
nmi.c	…
nmi_on_reset.S	…
prep_c.c	arm: set low exception vector location	2022-11-23 11:36:26 +01:00
swap.c	…
swap_helper.S	…
thread.c	arch/arm/core: fixup typo	2022-11-27 12:11:44 +01:00
userspace.S	…
vector_table.ld	…