52 lines
1.2 KiB
Plaintext
52 lines
1.2 KiB
Plaintext
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h>
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&iomuxc {
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iomuxc_uart2_rx_uart2_rx: IOMUXC_UART2_RX_UART2_RX {
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pinmux = <SC_P_UART2_RX IMX8QXP_DMA_LPUART2_RX_UART2_RX>;
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};
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iomuxc_uart2_tx_uart2_tx: IOMUXC_UART2_TX_UART2_TX {
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pinmux = <SC_P_UART2_TX IMX8QXP_DMA_LPUART2_TX_UART2_TX>;
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};
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iomuxc_adma_sai1_txfs_sai1_rxfs: IOMUXC_ADMA_SAI1_TXFS_SAI1_RXFS {
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pinmux = <SC_P_SAI1_RXFS IMX8QXP_ADMA_SAI1_TXFS_SAI1_RXFS>;
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};
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iomuxc_adma_sai1_rxd_sai1_rxd: IOMUXC_ADMA_SAI1_RXD_SAI1_RXD {
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pinmux = <SC_P_SAI1_RXD IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD>;
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};
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iomuxc_adma_sai1_txc_sai1_rxc: IOMUXC_ADMA_SAI1_TXC_SAI1_RXC {
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pinmux = <SC_P_SAI1_RXC IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC>;
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};
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iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 {
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pinmux = <SC_P_SPI0_CS1 IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1>;
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};
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};
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&pinctrl {
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lpuart2_default: lpuart2_default {
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group0 {
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pinmux = <&iomuxc_uart2_rx_uart2_rx>,
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<&iomuxc_uart2_tx_uart2_tx>;
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};
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};
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sai1_default: sai1_default {
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group0 {
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pinmux = <&iomuxc_adma_sai1_txfs_sai1_rxfs>,
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<&iomuxc_adma_sai1_rxd_sai1_rxd>,
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<&iomuxc_adma_sai1_txc_sai1_rxc>,
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<&iomuxc_adma_sai1_txd_spi0_cs1>;
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};
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};
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};
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