494 lines
16 KiB
C
494 lines
16 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ECSPI_H__
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#define __ECSPI_H__
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include "device_imx.h"
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/*!
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* @addtogroup ecspi_driver
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Channel select. */
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enum _ecspi_channel_select
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{
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ecspiSelectChannel0 = 0U, /*!< Select Channel 0. Chip Select 0 (SS0) is asserted.*/
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ecspiSelectChannel1 = 1U, /*!< Select Channel 1. Chip Select 1 (SS1) is asserted.*/
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ecspiSelectChannel2 = 2U, /*!< Select Channel 2. Chip Select 2 (SS2) is asserted.*/
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ecspiSelectChannel3 = 3U, /*!< Select Channel 3. Chip Select 3 (SS3) is asserted.*/
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};
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/*! @brief Channel mode. */
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enum _ecspi_master_slave_mode
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{
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ecspiSlaveMode = 0U, /*!< Set Slave Mode.*/
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ecspiMasterMode = 1U, /*!< Set Master Mode.*/
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};
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/*! @brief Clock phase. */
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enum _ecspi_clock_phase
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{
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ecspiClockPhaseFirstEdge = 0U, /*!< Data is captured on the leading edge of the SCK and
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changed on the following edge.*/
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ecspiClockPhaseSecondEdge = 1U, /*!< Data is changed on the leading edge of the SCK and
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captured on the following edge.*/
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};
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/*! @brief Clock polarity. */
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enum _ecspi_clock_polarity
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{
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ecspiClockPolarityActiveHigh = 0U, /*!< Active-high eCSPI clock (idles low).*/
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ecspiClockPolarityActiveLow = 1U, /*!< Active-low eCSPI clock (idles high).*/
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};
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/*! @brief SS signal polarity. */
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enum _ecspi_ss_polarity
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{
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ecspiSSPolarityActiveLow = 0U, /*!< Active-low, eCSPI SS signal.*/
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ecspiSSPolarityActiveHigh = 1U, /*!< Active-high, eCSPI SS signal.*/
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};
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/*! @brief Inactive state of data line. */
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enum _ecspi_dataline_inactivestate
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{
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ecspiDataLineStayHigh = 0U, /*!< Data line inactive state stay high.*/
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ecspiDataLineStayLow = 1U, /*!< Data line inactive state stay low.*/
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};
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/*! @brief Inactive state of SCLK. */
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enum _ecspi_sclk_inactivestate
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{
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ecspiSclkStayLow = 0U, /*!< SCLK inactive state stay low.*/
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ecspiSclkStayHigh = 1U, /*!< SCLK line inactive state stay high.*/
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};
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/*! @brief sample period counter clock source. */
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enum _ecspi_sampleperiod_clocksource
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{
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ecspiSclk = 0U, /*!< Sample period counter clock from SCLK.*/
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ecspiLowFreq32K = 1U, /*!< Sample period counter clock from from LFRC (32.768 KHz).*/
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};
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/*! @brief DMA Source definition. */
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enum _ecspi_dma_source
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{
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ecspiDmaTxfifoEmpty = 7U, /*!< TXFIFO Empty DMA Request.*/
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ecspiDmaRxfifoRequest = 23U, /*!< RXFIFO DMA Request.*/
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ecspiDmaRxfifoTail = 31U, /*!< RXFIFO TAIL DMA Request.*/
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};
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/*! @brief RXFIFO and TXFIFO threshold. */
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enum _ecspi_fifothreshold
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{
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ecspiTxfifoThreshold = 0U, /*!< Defines the FIFO threshold that triggers a TX DMA/INT request.*/
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ecspiRxfifoThreshold = 16U, /*!< defines the FIFO threshold that triggers a RX DMA/INT request.*/
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};
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/*! @brief Status flag. */
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enum _ecspi_status_flag
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{
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ecspiFlagTxfifoEmpty = 1U << 0, /*!< TXFIFO Empty Flag.*/
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ecspiFlagTxfifoDataRequest = 1U << 1, /*!< TXFIFO Data Request Flag.*/
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ecspiFlagTxfifoFull = 1U << 2, /*!< TXFIFO Full Flag.*/
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ecspiFlagRxfifoReady = 1U << 3, /*!< RXFIFO Ready Flag.*/
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ecspiFlagRxfifoDataRequest = 1U << 4, /*!< RXFIFO Data Request Flag.*/
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ecspiFlagRxfifoFull = 1U << 5, /*!< RXFIFO Full Flag.*/
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ecspiFlagRxfifoOverflow = 1U << 6, /*!< RXFIFO Overflow Flag.*/
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ecspiFlagTxfifoTc = 1U << 7, /*!< TXFIFO Transform Completed Flag.*/
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};
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/*! @brief Data Ready Control. */
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enum _ecspi_data_ready
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{
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ecspiRdyNoCare = 0U, /*!< The SPI_RDY signal is ignored.*/
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ecspiRdyFallEdgeTrig = 1U, /*!< Burst is triggered by the falling edge of the SPI_RDY signal (edge-triggered).*/
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ecspiRdyLowLevelTrig = 2U, /*!< Burst is triggered by a low level of the SPI_RDY signal (level-triggered).*/
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ecspiRdyReserved = 3U, /*!< Reserved.*/
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};
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/*! @brief Init structure. */
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typedef struct _ecspi_init_config
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{
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uint32_t clockRate; /*!< Specifies ECSPII module clock freq.*/
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uint32_t baudRate; /*!< Specifies desired eCSPI baud rate.*/
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uint32_t channelSelect; /*!< Specifies the channel select.*/
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uint32_t mode; /*!< Specifies the mode.*/
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uint32_t burstLength; /*!< Specifies the length of a burst to be transferred.*/
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uint32_t clockPhase; /*!< Specifies the clock phase.*/
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uint32_t clockPolarity; /*!< Specifies the clock polarity.*/
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bool ecspiAutoStart; /*!< Specifies the start mode.*/
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} ecspi_init_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name eCSPI Initialization and Configuration functions
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* @{
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*/
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/*!
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* @brief Initializes the eCSPI module.
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*
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* @param base eCSPI base pointer.
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* @param initConfig eCSPI initialization structure.
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*/
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void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig);
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/*!
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* @brief Enables the specified eCSPI module.
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*
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* @param base eCSPI base pointer.
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*/
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static inline void ECSPI_Enable(ECSPI_Type* base)
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{
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/* Enable the eCSPI. */
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ECSPI_CONREG_REG(base) |= ECSPI_CONREG_EN_MASK;
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}
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/*!
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* @brief Disable the specified eCSPI module.
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*
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* @param base eCSPI base pointer.
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*/
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static inline void ECSPI_Disable(ECSPI_Type* base)
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{
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/* Enable the eCSPI. */
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ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_EN_MASK;
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}
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/*!
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* @brief Insert the number of wait states to be inserted in data transfers.
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*
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* @param base eCSPI base pointer.
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* @param number the number of wait states.
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*/
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static inline void ECSPI_InsertWaitState(ECSPI_Type* base, uint32_t number)
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{
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/* Configure the number of wait states inserted. */
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ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)) |
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ECSPI_PERIODREG_SAMPLE_PERIOD(number);
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}
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/*!
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* @brief Set the clock source for the sample period counter.
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*
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* @param base eCSPI base pointer.
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* @param source The clock source (see @ref _ecspi_sampleperiod_clocksource enumeration).
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*/
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void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source);
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/*!
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* @brief Set the eCSPI clocks insert between the chip select active edge
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* and the first eCSPI clock edge.
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*
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* @param base eCSPI base pointer.
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* @param delay The number of wait states.
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*/
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static inline void ECSPI_SetDelay(ECSPI_Type* base, uint32_t delay)
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{
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/* Set the number of clocks insert. */
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ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_CSD_CTL_MASK)) |
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ECSPI_PERIODREG_CSD_CTL(delay);
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}
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/*!
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* @brief Set the inactive state of SCLK.
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*
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* @param base eCSPI base pointer.
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* @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration).
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* @param state SCLK inactive state (see @ref _ecspi_sclk_inactivestate enumeration).
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*/
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static inline void ECSPI_SetSCLKInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state)
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{
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/* Configure the inactive state of SCLK. */
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ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SCLK_CTL(1 << channel))) |
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ECSPI_CONFIGREG_SCLK_CTL((state & 1) << channel);
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}
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/*!
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* @brief Set the inactive state of data line.
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*
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* @param base eCSPI base pointer.
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* @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration).
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* @param state Data line inactive state (see @ref _ecspi_dataline_inactivestate enumeration).
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*/
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static inline void ECSPI_SetDataInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state)
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{
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/* Set the inactive state of Data Line. */
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ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_DATA_CTL(1 << channel))) |
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ECSPI_CONFIGREG_DATA_CTL((state & 1) << channel);
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}
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/*!
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* @brief Trigger a burst.
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*
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* @param base eCSPI base pointer.
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*/
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static inline void ECSPI_StartBurst(ECSPI_Type* base)
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{
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/* Start a burst. */
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ECSPI_CONREG_REG(base) |= ECSPI_CONREG_XCH_MASK;
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}
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/*!
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* @brief Set the burst length.
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*
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* @param base eCSPI base pointer.
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* @param length The value of burst length.
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*/
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static inline void ECSPI_SetBurstLength(ECSPI_Type* base, uint32_t length)
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{
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/* Set the burst length according to length. */
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ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_BURST_LENGTH_MASK)) |
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ECSPI_CONREG_BURST_LENGTH(length);
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}
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/*!
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* @brief Set eCSPI SS Wave Form.
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*
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* @param base eCSPI base pointer.
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* @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration).
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* @param ssMultiBurst For master mode, set true for multiple burst and false for one burst.
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* For slave mode, set true to complete burst by SS signal edges and false to complete
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* burst by number of bits received.
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*/
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static inline void ECSPI_SetSSMultipleBurst(ECSPI_Type* base, uint32_t channel, bool ssMultiBurst)
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{
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/* Set the SS wave form. */
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ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SS_CTL(1 << channel))) |
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ECSPI_CONFIGREG_SS_CTL(ssMultiBurst << channel);
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}
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/*!
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* @brief Set eCSPI SS Polarity.
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*
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* @param base eCSPI base pointer.
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* @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration).
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* @param polarity Set SS signal active logic (see @ref _ecspi_ss_polarity enumeration).
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*/
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static inline void ECSPI_SetSSPolarity(ECSPI_Type* base, uint32_t channel, uint32_t polarity)
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{
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/* Set the SS polarity. */
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ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SS_POL(1 << channel))) |
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ECSPI_CONFIGREG_SS_POL(polarity << channel);
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}
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/*!
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* @brief Set the Data Ready Control.
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*
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* @param base eCSPI base pointer.
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* @param spidataready eCSPI data ready control (see @ref _ecspi_data_ready enumeration).
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*/
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static inline void ECSPI_SetSPIDataReady(ECSPI_Type* base, uint32_t spidataready)
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{
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/* Set the Data Ready Control. */
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ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_DRCTL_MASK)) |
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ECSPI_CONREG_DRCTL(spidataready);
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}
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/*!
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* @brief Calculated the eCSPI baud rate in bits per second.
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* The calculated baud rate must not exceed the desired baud rate.
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*
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* @param base eCSPI base pointer.
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* @param sourceClockInHz eCSPI Clock(SCLK) (in Hz).
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* @param bitsPerSec the value of Baud Rate.
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* @return The calculated baud rate in bits-per-second, the nearest possible
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* baud rate without exceeding the desired baud rate.
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*/
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uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t bitsPerSec);
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/*@}*/
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/*!
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* @name Data transfers functions
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* @{
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*/
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/*!
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* @brief Transmits a data to TXFIFO.
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*
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* @param base eCSPI base pointer.
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* @param data Data to be transmitted.
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*/
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static inline void ECSPI_SendData(ECSPI_Type* base, uint32_t data)
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{
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/* Write data to Transmit Data Register. */
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ECSPI_TXDATA_REG(base) = data;
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}
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/*!
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* @brief Receives a data from RXFIFO.
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*
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* @param base eCSPI base pointer.
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* @return The value of received data.
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*/
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static inline uint32_t ECSPI_ReceiveData(ECSPI_Type* base)
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{
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/* Read data from Receive Data Register. */
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return ECSPI_RXDATA_REG(base);
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}
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/*!
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* @brief Read the number of words in the RXFIFO.
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*
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* @param base eCSPI base pointer.
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* @return The number of words in the RXFIFO.
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*/
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static inline uint32_t ECSPI_GetRxfifoCounter(ECSPI_Type* base)
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{
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/* Get the number of words in the RXFIFO. */
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return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT);
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}
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/*!
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* @brief Read the number of words in the TXFIFO.
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*
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* @param base eCSPI base pointer.
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* @return The number of words in the TXFIFO.
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*/
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static inline uint32_t ECSPI_GetTxfifoCounter(ECSPI_Type* base)
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{
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/* Get the number of words in the RXFIFO. */
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return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT);
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}
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/*@}*/
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/*!
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* @name DMA management functions
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* @{
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*/
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/*!
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* @brief Enable or disable the specified DMA Source.
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*
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* @param base eCSPI base pointer.
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* @param source specifies DMA source (see @ref _ecspi_dma_source enumeration).
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* @param enable Enable/Disable specified DMA Source.
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* - true: Enable specified DMA Source.
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* - false: Disable specified DMA Source.
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*/
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void ECSPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable);
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/*!
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* @brief Set the burst length of a DMA operation.
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*
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* @param base eCSPI base pointer.
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* @param length Specifies the burst length of a DMA operation.
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*/
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static inline void ECSPI_SetDMABurstLength(ECSPI_Type* base, uint32_t length)
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{
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/* Configure the burst length of a DMA operation. */
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ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_RX_DMA_LENGTH_MASK)) |
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ECSPI_DMAREG_RX_DMA_LENGTH(length);
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}
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/*!
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* @brief Set the RXFIFO or TXFIFO threshold.
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*
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* @param base eCSPI base pointer.
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* @param fifo Data transfer FIFO (see @ref _ecspi_fifothreshold enumeration).
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* @param threshold Threshold value.
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*/
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void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold);
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/*@}*/
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/*!
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* @name Interrupts and flags management functions
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* @{
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*/
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/*!
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* @brief Enable or disable the specified eCSPI interrupts.
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*
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* @param base eCSPI base pointer.
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* @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition).
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* @param enable Interrupt enable.
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* - true: Enable specified eCSPI interrupts.
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* - false: Disable specified eCSPI interrupts.
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*/
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void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable);
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/*!
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* @brief Checks whether the specified eCSPI flag is set or not.
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*
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* @param base eCSPI base pointer.
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* @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition).
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* @return eCSPI status, each bit represents one status flag.
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*/
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static inline uint32_t ECSPI_GetStatusFlag(ECSPI_Type* base, uint32_t flags)
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{
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/* return the vale of eCSPI status. */
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return ECSPI_STATREG_REG(base) & flags;
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}
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/*!
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* @brief Clear one or more eCSPI status flag.
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*
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* @param base eCSPI base pointer.
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* @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition).
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*/
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static inline void ECSPI_ClearStatusFlag(ECSPI_Type* base, uint32_t flags)
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{
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/* Write 1 to the status bit. */
|
|
ECSPI_STATREG_REG(base) = flags;
|
|
}
|
|
|
|
/*@}*/
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
/*! @} */
|
|
|
|
#endif /*__ECSPI_H__*/
|
|
|
|
/*******************************************************************************
|
|
* EOF
|
|
******************************************************************************/
|