Robert Winkler b18309c0d7 boards: doc: Add information about generating litex_vexriscv SoC ... This commit adds more information about the litex_vexrscv board target, including references to related projects and instruction about generating bitstream for the Digilent Arty A7-35T Board. Signed-off-by: Robert Winkler <rwinkler@antmicro.com>		2020-12-16 12:49:16 -05:00
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doc	boards: doc: Add information about generating litex_vexriscv SoC	2020-12-16 12:49:16 -05:00
CMakeLists.txt	…
Kconfig.board	…
Kconfig.defconfig	…
litex_vexriscv.dts	boards/dts: riscv: litex_vexriscv: add clock control driver to devicetree	2020-12-06 12:35:16 -05:00
litex_vexriscv.yaml	…
litex_vexriscv_defconfig	boards: riscv: litex_vexriscv: enable clock control driver	2020-12-06 12:35:16 -05:00