zephyr/dts/riscv
Jimmy Zheng 6caf803a41 dts: bindings: mbox: rename plic-sw to mbox-plic-sw
Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node
is based on the PLIC interrupt controller node instead using the plic
hardware directly.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2024-10-23 16:53:13 +02:00
..
andes dts: bindings: mbox: rename plic-sw to mbox-plic-sw 2024-10-23 16:53:13 +02:00
efinix dts: riscv: Fix incorrect plic size 2024-07-02 22:21:17 -04:00
espressif hotfix: drivers: i2s: update esp32s3/c3 I2S dtsi 2024-08-29 16:10:28 -04:00
gd
ite drivers: pinctrl: ITE: Add a property configure pin current strength 2024-06-06 00:41:35 -07:00
lowrisc
microchip
niosv
nordic soc: nordic: Remove the nRF54L15 EngA 2024-10-21 01:46:39 +01:00
openisa soc/openisa: enable the `C` extension 2024-07-03 15:06:14 -04:00
qemu dts: set the `riscv,isa` property for virt-based targets 2024-05-15 09:30:23 +02:00
sensry board: sensry: Add support for sy1xx 2024-09-16 20:19:31 +02:00
sifive
starfive
telink
neorv32.dtsi
renode_riscv32_virt.dtsi
riscv32-litex-vexriscv.dtsi drivers: watchdog: litex: add litex watchdog 2024-08-19 10:02:01 -04:00