187 lines
4.7 KiB
C
187 lines
4.7 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for nxp_lpc55s69 platform
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*
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* This module provides routines to initialize and support board-level
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* hardware for the nxp_lpc55s69 platform.
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/uart.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <aarch32/cortex_m/exc.h>
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#include <fsl_power.h>
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#include <fsl_clock.h>
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#include <fsl_common.h>
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#include <fsl_device_registers.h>
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#include <fsl_pint.h>
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/**
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*
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* @brief Initialize the system clock
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*
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* @return N/A
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*
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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#if defined(CONFIG_SOC_LPC55S16) || defined(CONFIG_SOC_LPC55S28) || \
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defined(CONFIG_SOC_LPC55S69_CPU0)
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/*!< Set up the clock sources */
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/*!< Configure FRO192M */
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/*!< Ensure FRO is on */
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POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
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/*!< Set up FRO to the 12 MHz, just for sure */
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CLOCK_SetupFROClocking(12000000U);
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/*!< Switch to FRO 12MHz first to ensure we can change the clock */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
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/* Enable FRO HF(96MHz) output */
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CLOCK_SetupFROClocking(96000000U);
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#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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/*!< Set FLASH wait states for core */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
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#endif
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
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/* Enables the clock for the I/O controller.: Enable Clock. */
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CLOCK_EnableClock(kCLOCK_Iocon);
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay)
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/* attach 12 MHz clock to FLEXCOMM4 */
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
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/* reset FLEXCOMM for I2C */
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RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(hs_lspi), okay)
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/* Attach 12 MHz clock to HSLSPI */
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CLOCK_AttachClk(kFRO_HF_DIV_to_HSLSPI);
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/* reset HSLSPI for SPI */
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RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn);
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)
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/* Enable 1 MHz FRO clock for WWDT */
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SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
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#endif
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#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mailbox0), nxp_lpc_mailbox, okay)
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CLOCK_EnableClock(kCLOCK_Mailbox);
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/* Reset the MAILBOX module */
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RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn);
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#endif
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#endif /* CONFIG_SOC_LPC55S69_CPU0 */
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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* @return 0
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*/
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static int nxp_lpc55xxx_init(const struct device *arg)
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{
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ARG_UNUSED(arg);
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/* old interrupt lock level */
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unsigned int oldLevel;
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/* disable interrupts */
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oldLevel = irq_lock();
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z_arm_clear_faults();
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/* Initialize FRO/system clock to 96 MHz */
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clock_init();
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#ifdef CONFIG_GPIO_MCUX_LPC
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/* Turn on PINT device*/
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PINT_Init(PINT);
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#endif
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/*
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* install default handler that simply resets the CPU if configured in
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* the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
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#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)
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/**
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*
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* @brief Second Core Init
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*
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* This routine boots the secondary core
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* @return N/A
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*/
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/* This function is also called at deep sleep resume. */
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int _second_core_init(const struct device *arg)
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{
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int32_t temp;
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ARG_UNUSED(arg);
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/* Setup the reset handler pointer (PC) and stack pointer value.
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* This is used once the second core runs its startup code.
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* The second core first boots from flash (address 0x00000000)
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* and then detects its identity (Core no. 1, second) and checks
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* registers CPBOOT and use them to continue the boot process.
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* Make sure the startup code for first core is
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* appropriate and shareable with the second core!
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*/
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SYSCON->CPUCFG |= SYSCON_CPUCFG_CPU1ENABLE_MASK;
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/* Boot source for Core 1 from flash */
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SYSCON->CPBOOT = SYSCON_CPBOOT_CPBOOT(DT_REG_ADDR(
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DT_CHOSEN(zephyr_code_cpu1_partition)));
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temp = SYSCON->CPUCTRL;
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temp |= 0xc0c48000;
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SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK |
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SYSCON_CPUCTRL_CPU1CLKEN_MASK;
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SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) &
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(~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
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return 0;
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}
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SYS_INIT(_second_core_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /*defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)*/
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