306 lines
15 KiB
C
306 lines
15 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_H
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#define SOC_H
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#include <sys/util.h>
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#include <toolchain.h>
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#ifndef _ASMLANGUAGE
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#include <devicetree.h>
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/* Interrupt Number Definition */
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typedef enum IRQn {
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/* CORTEX-M7 Processor Exceptions Numbers */
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NonMaskableInt_IRQn = -14, /*< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*< 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /*< 4 Cortex-M7 Memory Management Interrupt */
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BusFault_IRQn = -11, /*< 5 Cortex-M7 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*< 6 Cortex-M7 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*< 11 Cortex-M7 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*< 12 Cortex-M7 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*< 14 Cortex-M7 Pend SV Interrupt */
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SysTick_IRQn = -1, /*< 15 Cortex-M7 System Tick Interrupt */
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/* VIPER_MPU Specific Interrupt Numbers */
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M7_RESERVED_0 = 0,
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M7_MCU_AON_UART_INTR = 1,
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M7_MCU_AON_GPIO_INTR = 2,
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M7_CHIPCOMMONG_WDOG_RESET = 3,
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M7_RESERVED_4 = 4,
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M7_RESERVED_5 = 5,
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M7_MCU_SMBUS_INTR = 6,
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M7_MCU_TIMER_INTR = 7,
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M7_MCU_WDOG_INTR = 8,
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M7_MCU_ERROR_LOG_INTR = 9,
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M7_MCU_POWER_LOG_INTR = 10,
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M7_MCU_RESET_LOG_INTR = 11,
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M7_RESERVED_12 = 12,
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M7_RESERVED_13 = 13,
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M7_MCU_SECURITY_INTR = 14,
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M7_AVS_MONITOR_INTR = 15,
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M7_AVS_TEMP_RESET_INTR = 16,
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M7_GIC_AXI_ERR_INITR = 17,
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M7_GIC_ECC_ERR_INITR = 18,
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M7_RESERVED_19 = 19,
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M7_RESERVED_20 = 20,
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M7_RESERVED_21 = 21,
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M7_RESERVED_22 = 22,
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M7_RESERVED_23 = 23,
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M7_RESERVED_24 = 24,
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M7_MCU_MAILBOX1_EVENT = 25,
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M7_RESERVED_26 = 26,
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M7_RESERVED_27 = 27,
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M7_RESERVED_28 = 28,
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M7_MCU_IPROC_STANDBYWFE_EVENT = 29,
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M7_MCU_IPROC_STANDBYWFI_EVENT = 30,
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M7_MCU_MAILBOX_EVENT = 31,
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M7_MCU_TIMER1_INTR = 32,
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M7_MCU_TIMER2_INTR = 33,
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M7_MCU_COMB_IDM_INTR = 34,
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M7_RESERVED_35 = 35,
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M7_RESERVED_36 = 36,
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M7_RESERVED_37 = 37,
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M7_RESERVED_38 = 38,
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M7_RESERVED_39 = 39,
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M7_MCU_NS_MAILBOX0_EVENT = 40,
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M7_MCU_NS_MAILBOX1_EVENT = 41,
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M7_MCU_NS_MAILBOX2_EVENT = 42,
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M7_MCU_NS_MAILBOX3_EVENT = 43,
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M7_PCIE0_PERSTB_EVENT = 44,
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M7_PCIE1_PERSTB_EVENT = 45,
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M7_PCIE0_INB_PERSTB_EVENT = 46,
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M7_PCIE1_INB_PERSTB_EVENT = 47,
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M7_SSIM2_IRQ = 48,
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M7_SSIM2_AFBC_IRQ = 49,
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M7_SSIM2_AFBC_IRQ_AXI_ERR = 50,
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M7_SSIM2_AFBC_IRQ_CONFIG_SWAP = 51,
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M7_SSIM2_AFBC_IRQ_DECODE_ERR = 52,
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M7_SSIM2_AFBC_IRQ_DETLING_ERR = 53,
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M7_SSIM2_AFBC_IRQ_SECURE_ID_ERR = 54,
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M7_SSIM2_AFBC_IRQ_SURFACES_DONE = 55,
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M7_SSIM1_IRQ = 56,
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M7_SSIM1_AFBC_IRQ = 57,
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M7_SSIM1_AFBC_IRQ_AXI_ERR = 58,
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M7_SSIM1_AFBC_IRQ_CONFIG_SWAP = 59,
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M7_SSIM1_AFBC_IRQ_DECODE_ERR = 60,
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M7_SSIM1_AFBC_IRQ_DETLING_ERR = 61,
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M7_SSIM1_AFBC_IRQ_SECURE_ID_ERR = 62,
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M7_SSIM1_AFBC_IRQ_SURFACES_DONE = 63,
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M7_SSIM0_IRQ = 64,
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M7_SSIM0_AFBC_IRQ = 65,
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M7_SSIM0_AFBC_IRQ_AXI_ERR = 66,
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M7_SSIM0_AFBC_IRQ_CONFIG_SWAP = 67,
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M7_SSIM0_AFBC_IRQ_DECODE_ERR = 68,
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M7_SSIM0_AFBC_IRQ_DETLING_ERR = 69,
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M7_SSIM0_AFBC_IRQ_SECURE_ID_ERR = 70,
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M7_SSIM0_AFBC_IRQ_SURFACES_DONE = 71,
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M7_SCL1_IRQ = 72,
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M7_SCL0_IRQ = 73,
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M7_ENC2_IRQ = 74,
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M7_ENC1_IRQ = 75,
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M7_ENC0_IRQ = 76,
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M7_DEC1_IRQ = 77,
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M7_DEC0_IRQ = 78,
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M7_IHOST_CRM_INTERRUPT = 79,
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M7_IHOST_NEXTERRIRQ = 80,
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M7_IHOST_NINTERRIRQ = 81,
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M7_PAXB0_AXI_IBUF_INTR = 82,
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M7_PAXB0_GIC_INTR0 = 83,
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M7_PAXB0_GIC_INTR1 = 84,
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M7_PAXB0_GIC_INTR2 = 85,
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M7_PAXB0_GIC_INTR3 = 86,
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M7_PAXB0_GIC_INTR4 = 87,
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M7_PAXB0_GIC_INTR5 = 88,
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M7_PAXB0_GIC_MEM_ERR_INTR = 89,
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M7_PAXB0_MSIX_INTR0 = 90,
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M7_PAXB0_MSIX_INTR1 = 91,
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M7_PAXB0_MSIX_INTR2 = 92,
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M7_PAXB0_MSIX_INTR3 = 93,
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M7_PAXB0_MSIX_INTR4 = 94,
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M7_PAXB0_MSIX_INTR5 = 95,
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M7_PAXB0_MSIX_INTR6 = 96,
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M7_PAXB0_MSIX_INTR7 = 97,
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M7_PAXB0_MSIX_INTR8 = 98,
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M7_PAXB0_MSIX_INTR9 = 99,
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M7_PAXB0_MSIX_INTR10 = 100,
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M7_PAXB0_MSIX_INTR11 = 101,
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M7_PAXB0_MSIX_INTR12 = 102,
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M7_PAXB0_MSIX_INTR13 = 103,
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M7_PAXB0_MSIX_INTR14 = 104,
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M7_PAXB0_MSIX_INTR15 = 105,
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M7_PAXB1_AXI_IBUF_INTR = 106,
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M7_PAXB1_GIC_INTR0 = 107,
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M7_PAXB1_GIC_INTR1 = 108,
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M7_PAXB1_GIC_INTR2 = 109,
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M7_PAXB1_GIC_INTR3 = 110,
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M7_PAXB1_GIC_INTR4 = 111,
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M7_PAXB1_GIC_INTR5 = 112,
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M7_PAXB1_GIC_MEM_ERR_INTR = 113,
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M7_PAXB1_MSIX_INTR0 = 114,
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M7_PAXB1_MSIX_INTR1 = 115,
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M7_PAXB1_MSIX_INTR2 = 116,
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M7_PAXB1_MSIX_INTR3 = 117,
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M7_PAXB1_MSIX_INTR4 = 118,
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M7_PAXB1_MSIX_INTR5 = 119,
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M7_PAXB1_MSIX_INTR6 = 120,
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M7_PAXB1_MSIX_INTR7 = 121,
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M7_PAXB1_MSIX_INTR8 = 122,
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M7_PAXB1_MSIX_INTR9 = 123,
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M7_PAXB1_MSIX_INTR10 = 124,
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M7_PAXB1_MSIX_INTR11 = 125,
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M7_PAXB1_MSIX_INTR12 = 126,
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M7_PAXB1_MSIX_INTR13 = 127,
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M7_PAXB1_MSIX_INTR14 = 128,
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M7_PAXB1_MSIX_INTR15 = 129,
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M7_IRQ_PCIE_S0_PINS_BUS = 130,
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M7_IRQ_PCIE_S1_PINS_BUS = 131,
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M7_IRQ_PCIE_NIC_S_PINS_BUS = 132,
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M7_PCIE_GLOBAL_ERR_INTR = 133,
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M7_PCIE_ARB_ERR_INTR = 134,
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M7_PCIE_RM_ERR_INTR = 135,
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M7_VID_MSTR_RESP_ERR_INTR = 136,
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M7_SPI_RESERVED3_0 = 137,
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M7_SPI_RESERVED3_1 = 138,
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M7_SPI_RESERVED3_2 = 139,
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M7_SPI_RESERVED3_3 = 140,
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M7_IRQ_APB_SCR1_PINS_BUS = 141,
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M7_IRQ_APB_SCR2_PINS_BUS = 142,
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M7_IRQ_CRMU_M0_PINS_BUS = 143,
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M7_IRQ_CRMU_S0_PINS_BUS = 144,
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M7_IRQ_GIC_S0_PINS_BUS = 145,
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M7_SCR_SRAM_INTERRUPT = 146,
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M7_SRAM_TZC_INTERRUPT = 147,
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M7_PMON_INTERRUPT = 148,
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M7_SPI_RESERVED4_0 = 149,
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M7_DDR0_TZC_INTERRUPT = 150,
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M7_DDR1_TZC_INTERRUPT = 151,
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M7_DDR0_INTERRUPT0 = 152,
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M7_DDR0_INTERRUPT1 = 153,
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M7_DDR0_INTERRUPT2 = 154,
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M7_DDR0_INTERRUPT3 = 155,
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M7_DDR1_INTERRUPT0 = 156,
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M7_DDR1_INTERRUPT1 = 157,
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M7_DDR1_INTERRUPT2 = 158,
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M7_DDR1_INTERRUPT3 = 159,
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M7_SPI_RESERVED5_0 = 160,
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M7_SPI_RESERVED5_1 = 161,
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M7_SPI_RESERVED5_2 = 162,
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M7_SPI_RESERVED5_3 = 163,
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M7_SPI_RESERVED5_4 = 164,
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M7_SPI_RESERVED5_5 = 165,
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M7_SPI_RESERVED5_6 = 166,
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M7_SPI_RESERVED5_7 = 167,
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M7_DMAC_IRQ0 = 168,
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M7_DMAC_IRQ1 = 169,
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M7_DMAC_IRQ2 = 170,
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M7_DMAC_IRQ3 = 171,
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M7_DMAC_IRQ4 = 172,
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M7_DMAC_IRQ5 = 173,
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M7_DMAC_IRQ6 = 174,
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M7_DMAC_IRQ7 = 175,
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M7_DMAC_IRQ_ABORT = 176,
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M7_ETIMER_0_TM_INTR0 = 177,
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M7_ETIMER_0_TM_INTR1 = 178,
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M7_ETIMER_0_TM_INTR2 = 179,
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M7_ETIMER_0_TM_INTR3 = 180,
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M7_ETIMER_1_TM_INTR0 = 181,
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M7_ETIMER_1_TM_INTR1 = 182,
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M7_ETIMER_1_TM_INTR2 = 183,
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M7_ETIMER_1_TM_INTR3 = 184,
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M7_CHIPCOMMONG_MIIM_LINK_SCAN_STATUS_CHANGE_INTR = 185,
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M7_CHIPCOMMONG_MIIM_OP_DONE_INTR = 186,
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M7_CHIPCOMMONG_MIIM_PAUSE_SCAN_STATUS_CHANGE_INTR = 187,
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M7_CHIPCOMMONG_SMBUS0_INTR = 188,
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M7_CHIPCOMMONG_SMBUS1_INTR = 189,
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M7_CHIPCOMMONG_SPI0_INTR = 190,
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M7_CHIPCOMMONG_SPI1_INTR = 191,
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M7_CHIPCOMMONG_SPI2_INTR = 192,
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M7_CHIPCOMMONG_TIM0_INTR = 193,
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M7_CHIPCOMMONG_TIM1_INTR = 194,
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M7_CHIPCOMMONG_TIM2_INTR = 195,
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M7_CHIPCOMMONG_TIM3_INTR = 196,
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M7_CHIPCOMMONG_UART0_INTR = 197,
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M7_CHIPCOMMONG_UART1_INTR = 198,
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M7_CHIPCOMMONG_UART2_INTR = 199,
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M7_CHIPCOMMONG_UART3_INTR = 200,
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M7_CHIPCOMMONG_WDOG_INTR = 201,
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M7_CHIPCOMMONS_RNG_INTR = 202,
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M7_LS_GPIO_INTR = 203,
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M7_NAND_INTERRUPT_O = 204,
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M7_QSPI_INTERRUPT_O = 205,
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M7_IRQ_APB_LS1_PINS_BUS = 206,
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M7_IRQ_APB_LS2_PINS_BUS = 207,
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M7_IRQ_APB_LS3_PINS_BUS = 208,
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M7_IRQ_CORESIGHT_M0_PINS_BUS = 209,
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M7_DMA_ARB_ERR_INTR = 210,
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M7_IRQ_NAND_S0_PINS_BUS = 211,
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M7_IRQ_QSPI_S0_PINS_BUS = 212,
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M7_IRQ_ROM_S0_PINS_BUS = 213,
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M7_IRQ_SMAU_S0_PINS_BUS = 214,
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M7_SMU_INTR = 215,
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M7_SMU_DMU_PAR_ERR = 216,
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M7_SMU_DMU_AUTH_ERR = 217,
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M7_SPI_RESERVED6_0 = 218,
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M7_SPI_RESERVED6_1 = 219,
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M7_SPI_RESERVED6_2 = 220,
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M7_SPI_RESERVED6_3 = 221,
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M7_SPI_RESERVED6_4 = 222,
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M7_SPI_RESERVED6_5 = 223,
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M7_SPI_RESERVED6_6 = 224,
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M7_SPI_RESERVED6_7 = 225,
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M7_SPI_RESERVED6_8 = 226,
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M7_SPI_RESERVED6_9 = 227,
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M7_SPI_RESERVED6_10 = 228,
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M7_SPI_RESERVED6_11 = 229,
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M7_SPI_RESERVED6_12 = 230,
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M7_SPI_RESERVED6_13 = 231,
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M7_SPI_RESERVED7_0 = 232,
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M7_SPI_RESERVED7_1 = 233,
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M7_SPI_RESERVED7_2 = 234,
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M7_SPI_RESERVED7_3 = 235,
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M7_SPI_RESERVED7_4 = 236,
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M7_SPI_RESERVED7_5 = 237,
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M7_SPI_RESERVED7_6 = 238,
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M7_SPI_RESERVED7_7 = 239,
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} IRQn_Type;
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#endif
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/*
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* Processor and Core Peripheral Section
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*/
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/*
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* \brief Configuration of the CORTEX-M7 Processor and Core Peripherals
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*/
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#if defined(CONFIG_SOC_BCM58402_M7)
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#define __MPU_PRESENT 1
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#define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS
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#endif
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/* Registers block */
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#define CRMU_MCU_EXTRA_EVENT_STATUS 0x40070054
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#define CRMU_MCU_EXTRA_EVENT_CLEAR 0x4007005c
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#define CRMU_MCU_EXTRA_EVENT_MASK 0x40070064
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#define PCIE0_PERST_INTR BIT(4)
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#define PCIE0_PERST_INB_INTR BIT(6)
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#define PCIE_PERSTB_INTR_CTL_STS 0x400700f0
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#define PCIE0_PERST_FE_INTR BIT(1)
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#define PCIE0_PERST_INB_FE_INTR BIT(3)
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#define PMON_LITE_PCIE_BASE 0x48180000
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#define LS_ICFG_PMON_LITE_CLK_CTRL 0x482f00bc
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#define PCIE_PMON_LITE_CLK_ENABLE (BIT(0) | BIT(2))
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#define LS_ICFG_PMON_LITE_SW_RESETN 0x482f0120
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#define PCIE_PMON_LITE_SW_RESETN BIT(0)
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#endif
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