Kai Vehmanen 7fd0a7a5eb soc: intel_adsp: replace icache ISR workaround with custom idle solution ... A workaround to avoid icache corruption was added in commit be881d4cf2 ("arch: xtensa: add isync to interrupt vector"). This patch implements a different workaround by adding custom logic to idle entry on affected Intel ADSP platforms. To safely enter "waiti" when clock gating is enabled, we need to ensure icache is both unlocked and invalidated upon entry. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>		2024-04-15 16:26:39 +02:00
..
core	llext: xtensa: add support for in-place relocatable extensions	2024-04-11 11:35:24 -05:00
include	soc: intel_adsp: replace icache ISR workaround with custom idle solution	2024-04-15 16:26:39 +02:00
CMakeLists.txt	…
Kconfig	xtensa: mpu: introduce CONFIG_XTENSA_MPU_ONLY_SOC_RANGES	2024-03-19 22:17:34 -04:00