354 lines
8.6 KiB
C
354 lines
8.6 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <errno.h>
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#include <gpio.h>
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#include <board.h>
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#include "qm_ss_gpio.h"
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#include "qm_ss_isr.h"
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#include "ss_clk.h"
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#include "gpio_utils.h"
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struct ss_gpio_qmsi_config {
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qm_ss_gpio_t gpio;
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uint8_t num_pins;
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};
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struct ss_gpio_qmsi_runtime {
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sys_slist_t callbacks;
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uint32_t pin_callbacks;
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#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
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struct nano_sem sem;
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#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
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};
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#ifdef CONFIG_GPIO_QMSI_API_REENTRANCY
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#define RP_GET(dev) (&((struct ss_gpio_qmsi_runtime *)(dev->driver_data))->sem)
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static const int reentrancy_protection = 1;
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#else
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#define RP_GET(context) (NULL)
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static const int reentrancy_protection;
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#endif /* CONFIG_GPIO_QMSI_API_REENTRANCY */
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static void gpio_reentrancy_init(struct device *dev)
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{
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if (!reentrancy_protection) {
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return;
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}
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nano_sem_init(RP_GET(dev));
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nano_sem_give(RP_GET(dev));
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}
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static void gpio_critical_region_start(struct device *dev)
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{
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if (!reentrancy_protection) {
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return;
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}
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nano_sem_take(RP_GET(dev), TICKS_UNLIMITED);
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}
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static void gpio_critical_region_end(struct device *dev)
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{
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if (!reentrancy_protection) {
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return;
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}
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nano_sem_give(RP_GET(dev));
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}
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static int ss_gpio_qmsi_init(struct device *dev);
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#ifdef CONFIG_GPIO_QMSI_SS_0
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static const struct ss_gpio_qmsi_config ss_gpio_0_config = {
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.gpio = QM_SS_GPIO_0,
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.num_pins = QM_SS_GPIO_NUM_PINS,
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};
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static struct ss_gpio_qmsi_runtime ss_gpio_0_runtime;
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DEVICE_INIT(ss_gpio_0, CONFIG_GPIO_QMSI_SS_0_NAME, &ss_gpio_qmsi_init,
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&ss_gpio_0_runtime, &ss_gpio_0_config,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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#endif /* CONFIG_GPIO_QMSI_SS_0 */
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#ifdef CONFIG_GPIO_QMSI_SS_1
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static const struct ss_gpio_qmsi_config ss_gpio_1_config = {
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.gpio = QM_SS_GPIO_1,
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.num_pins = QM_SS_GPIO_NUM_PINS,
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};
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static struct ss_gpio_qmsi_runtime gpio_1_runtime;
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DEVICE_INIT(ss_gpio_1, CONFIG_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init,
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&gpio_1_runtime, &ss_gpio_1_config,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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#endif /* CONFIG_GPIO_QMSI_SS_1 */
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static void ss_gpio_qmsi_callback(void *data, uint32_t status)
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{
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struct device *port = data;
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struct ss_gpio_qmsi_runtime *context = port->driver_data;
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const uint32_t enabled_mask = context->pin_callbacks & status;
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if (enabled_mask) {
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_gpio_fire_callbacks(&context->callbacks, port, enabled_mask);
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}
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}
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static void ss_qmsi_write_bit(uint32_t *target, uint8_t bit, uint8_t value)
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{
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if (value) {
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sys_set_bit((uintptr_t) target, bit);
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} else {
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sys_clear_bit((uintptr_t) target, bit);
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}
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}
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static inline void ss_qmsi_pin_config(struct device *port, uint32_t pin,
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int flags)
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{
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const struct ss_gpio_qmsi_config *gpio_config =
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port->config->config_info;
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qm_ss_gpio_t gpio = gpio_config->gpio;
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uint32_t controller;
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qm_ss_gpio_port_config_t cfg = { 0 };
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switch (gpio) {
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#ifdef CONFIG_GPIO_QMSI_SS_0
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case QM_SS_GPIO_0:
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controller = QM_SS_GPIO_0_BASE;
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break;
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#endif /* CONFIG_GPIO_QMSI_SS_0 */
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#ifdef CONFIG_GPIO_QMSI_SS_1
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case QM_SS_GPIO_1:
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controller = QM_SS_GPIO_1_BASE;
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break;
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#endif /* CONFIG_GPIO_QMSI_SS_1 */
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default:
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return;
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}
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cfg.direction = __builtin_arc_lr(controller + QM_SS_GPIO_SWPORTA_DDR);
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cfg.int_en = __builtin_arc_lr(controller + QM_SS_GPIO_INTEN);
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cfg.int_type = __builtin_arc_lr(controller + QM_SS_GPIO_INTTYPE_LEVEL);
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cfg.int_polarity =
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__builtin_arc_lr(controller + QM_SS_GPIO_INT_POLARITY);
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cfg.int_debounce = __builtin_arc_lr(controller + QM_SS_GPIO_DEBOUNCE);
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cfg.callback = ss_gpio_qmsi_callback;
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cfg.callback_data = port;
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ss_qmsi_write_bit(&cfg.direction, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT) {
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ss_qmsi_write_bit(&cfg.int_type, pin, (flags & GPIO_INT_EDGE));
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ss_qmsi_write_bit(&cfg.int_polarity, pin,
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(flags & GPIO_INT_ACTIVE_HIGH));
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ss_qmsi_write_bit(&cfg.int_debounce, pin,
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(flags & GPIO_INT_DEBOUNCE));
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ss_qmsi_write_bit(&cfg.int_en, pin, 1);
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}
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gpio_critical_region_start(port);
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qm_ss_gpio_set_config(gpio, &cfg);
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gpio_critical_region_end(port);
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}
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static inline void ss_qmsi_port_config(struct device *port, int flags)
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{
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const struct ss_gpio_qmsi_config *gpio_config =
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port->config->config_info;
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uint8_t num_pins = gpio_config->num_pins;
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int i;
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for (i = 0; i < num_pins; i++) {
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ss_qmsi_pin_config(port, i, flags);
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}
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}
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static inline int ss_gpio_qmsi_config(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return -EINVAL;
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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ss_qmsi_pin_config(port, pin, flags);
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} else {
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ss_qmsi_port_config(port, flags);
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}
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return 0;
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}
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static inline int ss_gpio_qmsi_write(struct device *port, int access_op,
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uint32_t pin, uint32_t value)
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{
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const struct ss_gpio_qmsi_config *gpio_config =
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port->config->config_info;
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qm_ss_gpio_t gpio = gpio_config->gpio;
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gpio_critical_region_start(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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qm_ss_gpio_set_pin(gpio, pin);
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} else {
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qm_ss_gpio_clear_pin(gpio, pin);
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}
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} else {
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qm_ss_gpio_write_port(gpio, value);
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}
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gpio_critical_region_end(port);
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return 0;
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}
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static inline int ss_gpio_qmsi_read(struct device *port, int access_op,
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uint32_t pin, uint32_t *value)
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{
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const struct ss_gpio_qmsi_config *gpio_config =
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port->config->config_info;
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qm_ss_gpio_t gpio = gpio_config->gpio;
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qm_ss_gpio_state_t state;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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qm_ss_gpio_read_pin(gpio, pin, &state);
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*value = state;
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} else {
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qm_ss_gpio_read_port(gpio, value);
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}
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return 0;
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}
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static inline int ss_gpio_qmsi_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct ss_gpio_qmsi_runtime *context = port->driver_data;
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_gpio_manage_callback(&context->callbacks, callback, set);
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return 0;
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}
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static inline int ss_gpio_qmsi_enable_callback(struct device *port,
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int access_op, uint32_t pin)
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{
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struct ss_gpio_qmsi_runtime *context = port->driver_data;
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gpio_critical_region_start(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks |= BIT(pin);
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} else {
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context->pin_callbacks = 0xffffffff;
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}
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gpio_critical_region_end(port);
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return 0;
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}
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static inline int ss_gpio_qmsi_disable_callback(struct device *port,
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int access_op, uint32_t pin)
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{
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struct ss_gpio_qmsi_runtime *context = port->driver_data;
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gpio_critical_region_start(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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context->pin_callbacks &= ~BIT(pin);
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} else {
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context->pin_callbacks = 0;
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}
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gpio_critical_region_end(port);
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return 0;
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}
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static const struct gpio_driver_api api_funcs = {
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.config = ss_gpio_qmsi_config,
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.write = ss_gpio_qmsi_write,
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.read = ss_gpio_qmsi_read,
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.manage_callback = ss_gpio_qmsi_manage_callback,
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.enable_callback = ss_gpio_qmsi_enable_callback,
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.disable_callback = ss_gpio_qmsi_disable_callback,
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};
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void ss_gpio_isr(void *arg)
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{
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struct device *port = arg;
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const struct ss_gpio_qmsi_config *gpio_config =
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port->config->config_info;
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if (gpio_config->gpio == QM_SS_GPIO_0) {
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qm_ss_gpio_0_isr(NULL);
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} else {
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qm_ss_gpio_1_isr(NULL);
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}
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}
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static int ss_gpio_qmsi_init(struct device *port)
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{
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const struct ss_gpio_qmsi_config *gpio_config =
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port->config->config_info;
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uint32_t *scss_intmask = NULL;
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gpio_reentrancy_init(port);
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switch (gpio_config->gpio) {
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#ifdef CONFIG_GPIO_QMSI_SS_0
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case QM_SS_GPIO_0:
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IRQ_CONNECT(IRQ_GPIO0_INTR,
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CONFIG_GPIO_QMSI_SS_0_IRQ_PRI, ss_gpio_isr,
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DEVICE_GET(ss_gpio_0), 0);
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irq_enable(IRQ_GPIO0_INTR);
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ss_clk_gpio_enable(QM_SS_GPIO_0);
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scss_intmask =
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(uint32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_0_int_mask;
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*scss_intmask &= ~BIT(8);
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break;
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#endif /* CONFIG_GPIO_QMSI_SS_0 */
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#ifdef CONFIG_GPIO_QMSI_SS_1
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case QM_SS_GPIO_1:
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IRQ_CONNECT(IRQ_GPIO1_INTR,
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CONFIG_GPIO_QMSI_SS_1_IRQ_PRI, ss_gpio_isr,
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DEVICE_GET(ss_gpio_1), 0);
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irq_enable(IRQ_GPIO1_INTR);
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ss_clk_gpio_enable(QM_SS_GPIO_1);
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scss_intmask =
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(uint32_t *)&QM_INTERRUPT_ROUTER->ss_gpio_1_int_mask;
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*scss_intmask &= ~BIT(8);
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break;
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#endif /* CONFIG_GPIO_QMSI_SS_1 */
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default:
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return -EIO;
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}
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port->driver_api = &api_funcs;
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return 0;
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}
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