35 lines
874 B
ArmAsm
35 lines
874 B
ArmAsm
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* common interrupt management code for riscv SOCs supporting the riscv
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* privileged architecture specification
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*/
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#include <zephyr/kernel_structs.h>
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#include <offsets.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/arch/riscv/irq.h>
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/*
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* __soc_handle_irq is defined as .weak to allow re-implementation by
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* SOCs that do not truly follow the riscv privilege specification.
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*/
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WTEXT(__soc_handle_irq)
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/*
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* SOC-specific function to handle pending IRQ number generating the interrupt.
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* Exception number is given as parameter via register a0.
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*/
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SECTION_FUNC(exception.other, __soc_handle_irq)
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/* Clear exception number from CSR mip register */
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li t1, 1
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sll t0, t1, a0
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csrrc t1, mip, t0
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/* Return */
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ret
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