73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm64/arm_mmu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("GIC",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("GIC",
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DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
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DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("CCM",
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DT_REG_ADDR(DT_NODELABEL(ccm)),
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DT_REG_SIZE(DT_NODELABEL(ccm)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("ANA_PLL",
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DT_REG_ADDR(DT_NODELABEL(ana_pll)),
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DT_REG_SIZE(DT_NODELABEL(ana_pll)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("IOMUXC",
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DT_REG_ADDR(DT_NODELABEL(iomuxc)),
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DT_REG_SIZE(DT_NODELABEL(iomuxc)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_kinetis_lpuart,
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(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
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#if CONFIG_SOF
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MMU_REGION_FLAT_ENTRY("MU2_A",
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DT_REG_ADDR(DT_NODELABEL(mu2_a)),
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DT_REG_SIZE(DT_NODELABEL(mu2_a)),
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MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("OUTBOX",
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DT_REG_ADDR(DT_NODELABEL(outbox)),
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DT_REG_SIZE(DT_NODELABEL(outbox)),
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MT_NORMAL | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("INBOX",
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DT_REG_ADDR(DT_NODELABEL(inbox)),
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DT_REG_SIZE(DT_NODELABEL(inbox)),
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MT_NORMAL | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("STREAM",
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DT_REG_ADDR(DT_NODELABEL(stream)),
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DT_REG_SIZE(DT_NODELABEL(stream)),
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MT_NORMAL | MT_P_RW_U_NA | MT_NS),
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MMU_REGION_FLAT_ENTRY("HOST_RAM",
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DT_REG_ADDR(DT_NODELABEL(host_ram)),
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DT_REG_SIZE(DT_NODELABEL(host_ram)),
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MT_NORMAL | MT_P_RW_U_NA | MT_NS),
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#endif /* CONFIG_SOF */
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};
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