zephyr/dts/arm/st/f3/stm32f303Xb.dtsi

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/*
* Copyright (c) 2023 Martin Gritzan
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f303.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "zephyr,memory-region", "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(8)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
};
rtc@40002800 {
bbram: backup_regs {
compatible = "st,stm32-bbram";
st,backup-regs = <16>;
status = "disabled";
};
};
};
};