184 lines
4.5 KiB
Plaintext
184 lines
4.5 KiB
Plaintext
/*
|
|
* Copyright (c) 2017 I-SENSE group of ICCS
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#include <st/f3/stm32f3.dtsi>
|
|
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
|
|
|
|
/ {
|
|
soc {
|
|
compatible = "st,stm32f303", "st,stm32f3", "simple-bus";
|
|
|
|
usb: usb@40005c00 {
|
|
/* Remap USB_LP IRQ to enable use with CAN_1 */
|
|
interrupts = <75 0>;
|
|
};
|
|
|
|
i2c2: i2c@40005800 {
|
|
compatible = "st,stm32-i2c-v2";
|
|
clock-frequency = <I2C_BITRATE_STANDARD>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x40005800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
|
|
/* I2C clock source should always be defined,
|
|
* even for the default value
|
|
*/
|
|
<&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
|
|
interrupts = <33 0>, <34 0>;
|
|
interrupt-names = "event", "error";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@40003800 {
|
|
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x40003800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
|
interrupts = <36 5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@40003c00 {
|
|
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x40003c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
|
interrupts = <51 5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@40005000 {
|
|
compatible = "st,stm32-uart";
|
|
reg = <0x40005000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
|
resets = <&rctl STM32_RESET(APB1, 20U)>;
|
|
interrupts = <53 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pin-controller@48000000 {
|
|
|
|
gpioe: gpio@48001000 {
|
|
compatible = "st,stm32-gpio";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x48001000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
|
|
};
|
|
};
|
|
|
|
timers1: timers@40012c00 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40012c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
|
resets = <&rctl STM32_RESET(APB2, 11U)>;
|
|
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
|
interrupt-names = "brk", "up", "trgcom", "cc";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers4: timers@40000800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
|
resets = <&rctl STM32_RESET(APB1, 2U)>;
|
|
interrupts = <30 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers8: timers@40013400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40013400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
|
resets = <&rctl STM32_RESET(APB2, 13U)>;
|
|
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
|
interrupt-names = "brk", "up", "trgcom", "cc";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers20: timers@40015000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40015000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
|
resets = <&rctl STM32_RESET(APB2, 20U)>;
|
|
interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
|
|
interrupt-names = "brk", "up", "trgcom", "cc";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
adc1: adc@50000000 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x50000000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
vref-mv = <3000>;
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <2 3 5 8 20 62 182 602>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
|
|
adc2: adc@50000100 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x50000100 0x4c>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
vref-mv = <3000>;
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <2 3 5 8 20 62 182 602>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
};
|
|
|
|
smbus2: smbus2 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c2>;
|
|
status = "disabled";
|
|
};
|
|
};
|