86 lines
1.9 KiB
Plaintext
86 lines
1.9 KiB
Plaintext
/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f0/stm32f031.dtsi>
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/ {
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soc {
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compatible = "st,stm32f042", "st,stm32f0", "simple-bus";
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clocks {
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clk_hsi48: clk-hsi48 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(48)>;
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status = "disabled";
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};
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1, 17U)>;
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interrupts = <28 0>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <26 3>;
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status = "disabled";
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};
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can1: can@40006400 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006400 0x400>;
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interrupts = <30 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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sample-point = <875>;
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};
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
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resets = <&rctl STM32_RESET(APB2, 16U)>;
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interrupts = <20 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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usb: usb@40005c00 {
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compatible = "st,stm32-usb";
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reg = <0x40005c00 0x400>;
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interrupts = <31 0>;
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interrupt-names = "usb";
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num-bidir-endpoints = <8>;
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ram-size = <1024>;
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phys = <&usb_fs_phy>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
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<&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
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status = "disabled";
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};
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};
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usb_fs_phy: usbphy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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