zephyr/dts/arm/st/f0/stm32f031.dtsi

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/*
* Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
compatible = "st,stm32f031", "st,stm32f0", "simple-bus";
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
resets = <&rctl STM32_RESET(APB1, 0U)>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
};
};
rtc@40002800 {
bbram: backup_regs {
compatible = "st,stm32-bbram";
st,backup-regs = <5>;
status = "disabled";
};
};
};
die_temp: dietemp {
compatible = "st,stm32-temp-cal";
ts-cal1-addr = <0x1FFFF7B8>;
ts-cal2-addr = <0x1FFFF7C2>;
ts-cal1-temp = <30>;
ts-cal2-temp = <110>;
ts-cal-vrefanalog = <3300>;
io-channels = <&adc1 16>;
status = "disabled";
};
/* All STM32F0 series have ADC VBAT channel, except STM32F0x0 value line */
vbat: vbat {
compatible = "st,stm32-vbat";
ratio = <2>;
io-channels = <&adc1 18>;
status = "disabled";
};
};