63 lines
1.3 KiB
Plaintext
63 lines
1.3 KiB
Plaintext
/*
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* Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f0/stm32f0.dtsi>
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/ {
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soc {
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compatible = "st,stm32f031", "st,stm32f0", "simple-bus";
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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resets = <&rctl STM32_RESET(APB1, 0U)>;
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interrupts = <15 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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rtc@40002800 {
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bbram: backup_regs {
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compatible = "st,stm32-bbram";
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st,backup-regs = <5>;
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status = "disabled";
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};
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};
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};
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die_temp: dietemp {
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compatible = "st,stm32-temp-cal";
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ts-cal1-addr = <0x1FFFF7B8>;
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ts-cal2-addr = <0x1FFFF7C2>;
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ts-cal1-temp = <30>;
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ts-cal2-temp = <110>;
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ts-cal-vrefanalog = <3300>;
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io-channels = <&adc1 16>;
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status = "disabled";
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};
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/* All STM32F0 series have ADC VBAT channel, except STM32F0x0 value line */
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vbat: vbat {
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compatible = "st,stm32-vbat";
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ratio = <2>;
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io-channels = <&adc1 18>;
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status = "disabled";
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};
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};
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