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zephyr/dts/arm/st/c0/stm32c0.dtsi

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/*
* Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv6-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/stm32c0_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
#include <zephyr/dt-bindings/reset/stm32c0_reset.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "st,stm32c0-hsi-clock";
hsi-div = <1>;
clock-frequency = <DT_FREQ_M(48)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "st,stm32-lse-clock";
clock-frequency = <32768>;
driving-capability = <0>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
};
soc {
flash: flash-controller@40022000 {
compatible = "st,stm32-flash-controller";
reg = <0x40022000 0x400>;
interrupts = <3 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
write-block-size = <8>;
erase-block-size = <2048>;
/* maximum erase time(ms) for a 2K sector */
max-erase-time = <40>;
};
};
rcc: rcc@40021000 {
compatible = "st,stm32f0-rcc";
#clock-cells = <2>;
reg = <0x40021000 0x400>;
rctl: reset-controller {
compatible = "st,stm32-rcc-rctl";
#reset-cells = <1>;
};
};
exti: interrupt-controller@40021800 {
compatible = "st,stm32g0-exti", "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
reg = <0x40021800 0x400>;
num-lines = <16>;
interrupts = <5 0>, <6 0>, <7 0>;
interrupt-names = "line0-1", "line2-3", "line4-15";
line-ranges = <0 2>, <2 2>, <4 12>;
};
pinctrl: pin-controller@50000000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x50000000 0x2000>;
gpioa: gpio@50000000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
};
gpiob: gpio@50000400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
};
gpioc: gpio@50000800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
};
gpiof: gpio@50001400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x50001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
interrupts = <2 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
prescaler = <32768>;
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
interrupts = <0 2>;
status = "disabled";
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
status = "disabled";
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
resets = <&rctl STM32_RESET(APB1H, 14U)>;
interrupts = <27 0>;
status = "disabled";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <28 0>;
status = "disabled";
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
resets = <&rctl STM32_RESET(APB1H, 11U)>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
resets = <&rctl STM32_RESET(APB1L, 1U)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;
resets = <&rctl STM32_RESET(APB1H, 15U)>;
interrupts = <19 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers16: timers@40014400 {
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
resets = <&rctl STM32_RESET(APB1H, 17U)>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers17: timers@40014800 {
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
resets = <&rctl STM32_RESET(APB1H, 18U)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <23 0>;
interrupt-names = "combined";
status = "disabled";
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;
interrupts = <12 0>;
status = "disabled";
#io-channel-cells = <1>;
resolutions = <STM32_ADC_RES(12, 0x00)
STM32_ADC_RES(10, 0x01)
STM32_ADC_RES(8, 0x02)
STM32_ADC_RES(6, 0x03)>;
sampling-times = <2 4 8 13 20 40 80 161>;
num-sampling-time-common-channels = <2>;
st,adc-sequencer = <NOT_FULLY_CONFIGURABLE>;
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2";
#dma-cells = <3>;
reg = <0x40020000 0x400>;
interrupts = <9 0 10 0 10 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
dma-requests = <3>;
dma-offset = <0>;
status = "disabled";
};
/* DMAMUX clock is enabled as long as DMA1 is enabled */
dmamux1: dmamux@40020800 {
compatible = "st,stm32-dmamux";
#dma-cells = <3>;
reg = <0x40020800 0x800>;
interrupts = <11 0>;
dma-channels = <3>;
dma-generators = <4>;
dma-requests= <49>;
status = "disabled";
};
};
die_temp: dietemp {
compatible = "st,stm32c0-temp-cal";
ts-cal1-addr = <0x1FFF7568>;
ts-cal1-temp = <30>;
ts-cal-vrefanalog = <3000>;
avgslope = <2530>;
io-channels = <&adc1 9>;
status = "disabled";
};
vref: vref {
compatible = "st,stm32-vref";
vrefint-cal-addr = <0x1FFF756A>;
vrefint-cal-mv = <3000>;
io-channels = <&adc1 10>;
status = "disabled";
};
smbus1: smbus1 {
compatible = "st,stm32-smbus";
#address-cells = <1>;
#size-cells = <0>;
i2c = <&i2c1>;
status = "disabled";
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};
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