292 lines
6.3 KiB
Plaintext
292 lines
6.3 KiB
Plaintext
/*
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* Copyright (c) 2020 Linumiz
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* Author: Parthiban Nallathambi <parthiban@linumiz.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/gpio/infineon-xmc4xxx-gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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flash_controller: flash_controller@58001000 {
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compatible = "infineon,xmc4xxx-flash-controller";
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reg = <0x58001000 0x1400>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@c000000 {
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compatible = "infineon,xmc4xxx-nv-flash","soc-nv-flash";
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write-block-size = <256>;
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};
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <120000000>;
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#clock-cells = <0>;
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};
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soc {
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intc: eru@40044000 {
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compatible = "infineon,xmc4xxx-intc";
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reg = <0x40044000 0xff>, <0x50004800 0xff>;
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/* naming order is intentional. eru1 maps to a lower address than eru0 */
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reg-names = "eru1", "eru0";
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interrupts = <1 1>, <2 1>, <3 1>, <4 1>, <5 1>, <6 1>, <7 1>, <8 1>;
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interrupt-names = "eru0sr0", "eru0sr1", "eru0sr2", "eru0sr3",
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"eru1sr0", "eru1sr1", "eru1sr2", "eru1sr3";
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};
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pinctrl: pinctrl@48028000 {
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compatible = "infineon,xmc4xxx-pinctrl";
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reg = <0x48028000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpio0: gpio@48028000 {
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compatible = "infineon,xmc4xxx-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48028000 0x100>;
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status = "disabled";
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};
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gpio1: gpio@48028100 {
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compatible = "infineon,xmc4xxx-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48028100 0x100>;
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status = "disabled";
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};
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gpio2: gpio@48028200 {
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compatible = "infineon,xmc4xxx-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48028200 0x100>;
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status = "disabled";
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};
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gpio14: gpio@48028e00 {
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compatible = "infineon,xmc4xxx-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48028e00 0x100>;
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status = "disabled";
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};
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gpio15: gpio@48028f00 {
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compatible = "infineon,xmc4xxx-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48028f00 0x100>;
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status = "disabled";
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};
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};
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dma0: dma0@50014000{
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compatible = "infineon,xmc4xxx-dma";
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reg = <0x50014000 0x2bc>;
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interrupts = <105 1>;
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dma-channels = <8>;
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#dma-cells = <3>;
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status = "disabled";
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};
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dma1: dma1@50018000 {
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compatible = "infineon,xmc4xxx-dma";
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reg = <0x50018000 0x15c>;
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interrupts = <110 1>;
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dma-channels = <4>;
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#dma-cells = <3>;
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status = "disabled";
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};
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usic0ch0: usic@40030000 {
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reg = <0x40030000 0x1ff>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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usic0ch1: usic@40030200 {
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reg = <0x40030200 0x1ff>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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usic1ch0: usic@48020000 {
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reg = <0x48020000 0x1ff>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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usic1ch1: usic@48020200 {
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reg = <0x48020200 0x1ff>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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usic2ch0: usic@48024000 {
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reg = <0x48024000 0x1ff>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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usic2ch1: usic@48024200 {
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reg = <0x48024200 0x1ff>;
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clocks = <&sysclk>;
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status = "disabled";
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};
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adc0: adc@40004400 {
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compatible = "infineon,xmc4xxx-adc";
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reg = <0x40004400 0x400>;
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interrupts = <18 62>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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adc1: adc@40004800 {
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compatible = "infineon,xmc4xxx-adc";
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reg = <0x40004800 0x400>;
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interrupts = <22 62>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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adc2: adc@40004c00 {
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compatible = "infineon,xmc4xxx-adc";
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reg = <0x40004C00 0x400>;
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interrupts = <26 62>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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adc3: adc@40005000 {
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compatible = "infineon,xmc4xxx-adc";
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reg = <0x40005000 0x400>;
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interrupts = <30 62>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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die_temp: die_temp@5000408c {
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reg = <0x5000408c 0x8>;
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compatible = "infineon,xmc4xxx-temp";
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status = "disabled";
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};
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pwm_ccu40: ccu40@4000c000 {
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compatible = "infineon,xmc4xxx-ccu4-pwm";
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reg = <0x4000c000 0x4000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ccu41: ccu41@40010000 {
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compatible = "infineon,xmc4xxx-ccu4-pwm";
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reg = <0x40010000 0x4000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ccu42: ccu42@40014000 {
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compatible = "infineon,xmc4xxx-ccu4-pwm";
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reg = <0x40014000 0x4000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ccu43: ccu43@48004000 {
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compatible = "infineon,xmc4xxx-ccu4-pwm";
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reg = <0x48004000 0x4000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ccu80: ccu80@40020000 {
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compatible = "infineon,xmc4xxx-ccu8-pwm";
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reg = <0x40020000 0x4000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_ccu81: ccu81@40024000 {
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compatible = "infineon,xmc4xxx-ccu8-pwm";
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reg = <0x40024000 0x4000>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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wdt0: watchdog@50008000 {
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compatible = "infineon,xmc4xxx-watchdog";
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reg = <0x50008000 0x4000>;
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interrupts = <0 1>;
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status = "disabled";
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};
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ethernet@5000c000 {
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reg = <0x5000C000 0x3FFF>;
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eth: ethernet {
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compatible = "infineon,xmc4xxx-ethernet";
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interrupts = <108 1>;
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status = "disabled";
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};
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mdio: mdio {
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compatible = "infineon,xmc4xxx-mdio";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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can: can@48014000 {
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compatible = "infineon,xmc4xxx-can";
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reg = <0x48014000 0x4000>;
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clock-prescaler = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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can_node0: can_node0@48014200 {
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compatible = "infineon,xmc4xxx-can-node";
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reg = <0x48014200 0x100>;
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interrupts = <76 1>;
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status = "disabled";
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};
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can_node1: can_node1@48014300 {
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compatible = "infineon,xmc4xxx-can-node";
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reg = <0x48014300 0x100>;
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interrupts = <77 1>;
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status = "disabled";
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};
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can_node2: can_node2@48014400 {
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compatible = "infineon,xmc4xxx-can-node";
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reg = <0x48014400 0x100>;
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interrupts = <78 1>;
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status = "disabled";
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <6>;
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};
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