069bcbcb7f
This adds new NXP mailbox driver for MBOX device. NXP mailbox IP driver supports sending data between cores. It uses 32 bit register to trigger irq to other core. This driver implementation uses 4 bits for channel selection of triggering mode, 4 bits for channel selection of data transfer and rest 24 bits for data. NXP mailbox IP Reference Manual UM11126, Chapter 52. https://www.nxp.com/webapp/Download?colCode=UM11126 Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com> |
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| .. | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.andes | ||
| Kconfig.nrfx | ||
| Kconfig.nxp_imx | ||
| Kconfig.nxp_mailbox | ||
| Kconfig.nxp_s32 | ||
| mbox_andes_plic_sw.c | ||
| mbox_handlers.c | ||
| mbox_nrfx_ipc.c | ||
| mbox_nxp_imx_mu.c | ||
| mbox_nxp_mailbox.c | ||
| mbox_nxp_s32_mru.c | ||