929 lines
22 KiB
Plaintext
929 lines
22 KiB
Plaintext
/*
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* Copyright (c) 2018 Yurii Hamann
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* Copyright (c) 2019 Centaur Analytics, Inc
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* Copyright (c) 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/stm32f7_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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#include <zephyr/dt-bindings/dma/stm32_dma.h>
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#include <zephyr/dt-bindings/adc/stm32f4_adc.h>
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#include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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quadspi_memory: memory-placeholder@90000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x90000000 DT_SIZE_M(256)>;
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zephyr,memory-region = "QSPI_PLACEHOLDER";
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zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32f7-pll-clock";
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status = "disabled";
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};
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};
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mcos {
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mco1: mco1 {
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compatible = "st,stm32-clock-mco";
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status = "disabled";
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};
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mco2: mco2 {
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compatible = "st,stm32-clock-mco";
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status = "disabled";
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};
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};
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soc {
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fmc: memory-controller@a0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xa0000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
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status = "disabled";
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sdram: sdram {
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compatible = "st,stm32-fmc-sdram";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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flash: flash-controller@40023c00 {
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compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller";
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reg = <0x40023c00 0x400>;
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interrupts = <4 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <1>;
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/* maximum erase time (ms) for a 256K sector */
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max-erase-time = <4000>;
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};
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};
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rcc: rcc@40023800 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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reg = <0x40023800 0x400>;
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rctl: reset-controller {
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compatible = "st,stm32-rcc-rctl";
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#reset-cells = <1>;
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};
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};
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exti: interrupt-controller@40013c00 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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reg = <0x40013c00 0x400>;
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num-lines = <16>;
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interrupts = <6 0>, <7 0>, <8 0>, <9 0>,
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<10 0>, <23 0>, <40 0>;
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interrupt-names = "line0", "line1", "line2", "line3",
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"line4", "line5-9", "line10-15";
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line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
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<4 1>, <5 5>, <10 6>;
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};
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pinctrl: pin-controller@40020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x40020000 0x2400>;
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gpioa: gpio@40020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
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};
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gpiob: gpio@40020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
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};
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gpioc: gpio@40020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
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};
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gpiod: gpio@40020C00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40020C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
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};
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gpioe: gpio@40021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
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};
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gpiof: gpio@40021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
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};
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gpiog: gpio@40021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
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};
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gpioh: gpio@40021C00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40021C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
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};
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gpioi: gpio@40022000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
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};
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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};
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usart1: serial@40011000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
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resets = <&rctl STM32_RESET(APB2, 4U)>;
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interrupts = <37 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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resets = <&rctl STM32_RESET(APB1, 17U)>;
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interrupts = <38 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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resets = <&rctl STM32_RESET(APB1, 18U)>;
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interrupts = <39 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible ="st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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resets = <&rctl STM32_RESET(APB1, 19U)>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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resets = <&rctl STM32_RESET(APB1, 20U)>;
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interrupts = <53 0>;
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status = "disabled";
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};
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usart6: serial@40011400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
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resets = <&rctl STM32_RESET(APB2, 5U)>;
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interrupts = <71 0>;
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status = "disabled";
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};
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uart7: serial@40007800 {
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compatible = "st,stm32-uart";
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reg = <0x40007800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
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resets = <&rctl STM32_RESET(APB1, 30U)>;
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interrupts = <82 0>;
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status = "disabled";
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};
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uart8: serial@40007c00 {
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compatible = "st,stm32-uart";
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reg = <0x40007c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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resets = <&rctl STM32_RESET(APB1, 31U)>;
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interrupts = <83 0>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c3: i2c@40005c00 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
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interrupts = <72 0>, <73 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 5>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <84 5>;
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status = "disabled";
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};
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spi5: spi@40015000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <85 5>;
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status = "disabled";
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};
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can1: can@40006400 {
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compatible = "st,stm32-bxcan";
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reg = <0x40006400 0x400>;
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interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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};
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timers1: timers@40010000 {
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
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resets = <&rctl STM32_RESET(APB2, 0U)>;
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interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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resets = <&rctl STM32_RESET(APB1, 0U)>;
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interrupts = <28 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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resets = <&rctl STM32_RESET(APB1, 1U)>;
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interrupts = <29 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "st,stm32-counter";
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status = "disabled";
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};
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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resets = <&rctl STM32_RESET(APB1, 2U)>;
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interrupts = <30 0>;
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interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers5: timers@40000c00 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40000c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
|
resets = <&rctl STM32_RESET(APB1, 3U)>;
|
|
interrupts = <50 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers6: timers@40001000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
|
resets = <&rctl STM32_RESET(APB1, 4U)>;
|
|
interrupts = <54 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers7: timers@40001400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
|
resets = <&rctl STM32_RESET(APB1, 5U)>;
|
|
interrupts = <55 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers8: timers@40010400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40010400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
|
|
resets = <&rctl STM32_RESET(APB2, 1U)>;
|
|
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
|
interrupt-names = "brk", "up", "trgcom", "cc";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
};
|
|
|
|
timers9: timers@40014000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
|
resets = <&rctl STM32_RESET(APB2, 16U)>;
|
|
interrupts = <24 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers10: timers@40014400 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
|
resets = <&rctl STM32_RESET(APB2, 17U)>;
|
|
interrupts = <25 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers11: timers@40014800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
|
resets = <&rctl STM32_RESET(APB2, 18U)>;
|
|
interrupts = <26 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers12: timers@40001800 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
|
resets = <&rctl STM32_RESET(APB1, 6U)>;
|
|
interrupts = <43 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers13: timers@40001c00 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40001c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
|
resets = <&rctl STM32_RESET(APB1, 7U)>;
|
|
interrupts = <44 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers14: timers@40002000 {
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40002000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
|
resets = <&rctl STM32_RESET(APB1, 8U)>;
|
|
interrupts = <45 0>;
|
|
interrupt-names = "global";
|
|
st,prescaler = <0>;
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <3>;
|
|
};
|
|
|
|
counter {
|
|
compatible = "st,stm32-counter";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usbotg_fs: usb@50000000 {
|
|
compatible = "st,stm32-otgfs";
|
|
reg = <0x50000000 0x40000>;
|
|
interrupts = <67 0>;
|
|
interrupt-names = "otgfs";
|
|
num-bidir-endpoints = <6>;
|
|
ram-size = <1280>;
|
|
maximum-speed = "full-speed";
|
|
phys = <&otgfs_phy>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
|
|
<&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_hs: usb@40040000 {
|
|
compatible = "st,stm32-otghs";
|
|
reg = <0x40040000 0x40000>;
|
|
interrupts = <77 0>, <74 0>, <75 0>;
|
|
interrupt-names = "otghs", "ep1_out", "ep1_in";
|
|
num-bidir-endpoints = <9>;
|
|
ram-size = <4096>;
|
|
maximum-speed = "full-speed";
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
|
|
<&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
|
|
phys = <&otghs_fs_phy>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@40002800 {
|
|
compatible = "st,stm32-rtc";
|
|
reg = <0x40002800 0x300>;
|
|
interrupts = <41 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
|
|
prescaler = <32768>;
|
|
alarms-count = <2>;
|
|
alrm-exti-line = <17>;
|
|
status = "disabled";
|
|
|
|
bbram: backup_regs {
|
|
compatible = "st,stm32-bbram";
|
|
st,backup-regs = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
adc1: adc@40012000 {
|
|
compatible = "st,stm32f4-adc", "st,stm32-adc";
|
|
reg = <0x40012000 0x50>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <3 15 28 56 84 112 144 480>;
|
|
st,adc-clock-source = <SYNC>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
|
|
adc2: adc@40012100 {
|
|
compatible = "st,stm32f4-adc", "st,stm32-adc";
|
|
reg = <0x40012100 0x50>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <3 15 28 56 84 112 144 480>;
|
|
st,adc-clock-source = <SYNC>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
|
|
adc3: adc@40012200 {
|
|
compatible = "st,stm32f4-adc", "st,stm32-adc";
|
|
reg = <0x40012200 0x50>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
|
|
interrupts = <18 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
resolutions = <STM32_ADC_RES(12, 0x00)
|
|
STM32_ADC_RES(10, 0x01)
|
|
STM32_ADC_RES(8, 0x02)
|
|
STM32_ADC_RES(6, 0x03)>;
|
|
sampling-times = <3 15 28 56 84 112 144 480>;
|
|
st,adc-clock-source = <SYNC>;
|
|
st,adc-sequencer = <FULLY_CONFIGURABLE>;
|
|
};
|
|
|
|
dac1: dac@40007400 {
|
|
compatible = "st,stm32-dac";
|
|
reg = <0x40007400 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
dma1: dma@40026000 {
|
|
compatible = "st,stm32-dma-v1";
|
|
#dma-cells = <4>;
|
|
reg = <0x40026000 0x400>;
|
|
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dma2: dma@40026400 {
|
|
compatible = "st,stm32-dma-v1";
|
|
#dma-cells = <4>;
|
|
reg = <0x40026400 0x400>;
|
|
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
|
|
st,mem2mem;
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@50060800 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x50060800 0x400>;
|
|
interrupts = <80 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>,
|
|
<&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc1: sdmmc@40012c00 {
|
|
compatible = "st,stm32-sdmmc";
|
|
reg = <0x40012c00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
|
|
<&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>;
|
|
resets = <&rctl STM32_RESET(APB2, 11U)>;
|
|
interrupts = <49 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
backup_sram: memory@40024000 {
|
|
compatible = "zephyr,memory-region", "st,stm32-backup-sram";
|
|
reg = <0x40024000 DT_SIZE_K(4)>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
|
zephyr,memory-region = "BACKUP_SRAM";
|
|
status = "disabled";
|
|
};
|
|
|
|
quadspi: quadspi@a0001000 {
|
|
compatible = "st,stm32-qspi";
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
reg = <0xa0001000 0x34>;
|
|
interrupts = <92 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
die_temp: dietemp {
|
|
compatible = "st,stm32-temp-cal";
|
|
ts-cal1-addr = <0x1FF0F44C>;
|
|
ts-cal2-addr = <0x1FF0F44E>;
|
|
ts-cal1-temp = <30>;
|
|
ts-cal2-temp = <110>;
|
|
ts-cal-vrefanalog = <3300>;
|
|
io-channels = <&adc1 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vref: vref {
|
|
compatible = "st,stm32-vref";
|
|
vrefint-cal-addr = <0x1FF0F44A>;
|
|
vrefint-cal-mv = <3300>;
|
|
io-channels = <&adc1 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vbat: vbat {
|
|
compatible = "st,stm32-vbat";
|
|
ratio = <4>;
|
|
io-channels = <&adc1 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
otghs_fs_phy: otghs_fs_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
otgfs_phy: otgfs_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
smbus1: smbus1 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
smbus2: smbus2 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
smbus3: smbus3 {
|
|
compatible = "st,stm32-smbus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c = <&i2c3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|