e8b6b86704
Currently all IO APIC interrupts are configured at fixed delivery mode, which is good for HEPT timer interrupt but it imposes burdens to device drivers to properly handle the repeated interrupt sent to all processors. This patch makes it more flexible so that device drivers can specify the delivery mode it desires in the IRQ connect APIs. - Don't hard code IOAPIC_FIXED in z_ioapic_irq_set(), meaning the IRQ delivery mode is passed in from the 'flags' argument and individual device driver needs to choose delivery mode for its own IO APIC interrupt. - To support different delivery mode in different IO APIC interrupts, need to save and restore RTE[10:8] during IOAPIC suspend and resume. If device driver doesn't pass either IOAPIC_FIXED or IOAPIC_LOWEST in IRQ_CONNECT()/irq_connect_dynamic() alike APIs, the delivery mode bit fields in the target RTE register are '0' which implies fixed mode. If the device driver wants the interrupt to be delivered to one CPU only, it needs to explicitly specify IOAPIC_LOWEST in one of the IRQ connect APIs. Signed-off-by: Zide Chen <zide.chen@intel.com> |
||
|---|---|---|
| .. | ||
| CMakeLists.txt | ||
| Kconfig | ||
| Kconfig.cavs | ||
| Kconfig.dw | ||
| Kconfig.gic | ||
| Kconfig.loapic | ||
| Kconfig.multilevel | ||
| Kconfig.multilevel.aggregator_template | ||
| Kconfig.rv32m1 | ||
| Kconfig.sam0 | ||
| Kconfig.shared_irq | ||
| Kconfig.stm32 | ||
| intc_arcv2_irq_unit.c | ||
| intc_cavs.c | ||
| intc_cavs.h | ||
| intc_dw.c | ||
| intc_dw.h | ||
| intc_exti_stm32.c | ||
| intc_gic.c | ||
| intc_gic_common_priv.h | ||
| intc_gicv3.c | ||
| intc_gicv3_priv.h | ||
| intc_ioapic.c | ||
| intc_ioapic_priv.h | ||
| intc_loapic.c | ||
| intc_loapic_spurious.S | ||
| intc_plic.c | ||
| intc_rv32m1_intmux.c | ||
| intc_sam0_eic.c | ||
| intc_sam0_eic_priv.h | ||
| intc_shared_irq.c | ||
| intc_swerv_pic.c | ||
| intc_system_apic.c | ||
| intc_vexriscv_litex.c | ||