101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* Copyright (c) 2020 Seagate Technology LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LPC11U6X_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_LPC11U6X_PINCTRL_H_
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/**
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* @brief Pin control register for standard digital I/O pins:
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*
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* [0:2] function.
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* [3:4] mode.
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* [5] hysteresis.
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* [6] invert input.
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* [7:9] reserved.
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* [10] open-drain mode.
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* [11:12] digital filter sample mode.
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* [13:15] clock divisor.
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* [16:31] reserved.
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*/
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/**
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* @brief Control registers for digital/analog I/O pins:
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*
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* [0:2] function.
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* [3:4] mode.
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* [5] hysteresis.
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* [6] invert input.
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* [7] analog mode.
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* [8] input glitch filter.
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* [9] reserved.
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* [10] open-drain mode.
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* [11:12] digital filter sample mode.
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* [13:15] clock divisor.
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* [16:31] reserved.
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*/
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/**
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* @brief Control registers for open-drain I/O pins (I2C):
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*
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* [0:2] function.
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* [3:7] reserved.
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* [8:9] I2C mode.
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* [10] reserved.
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* [11:12] digital filter sample mode.
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* [13:15] clock divisor.
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* [16:31] reserved.
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*/
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#define IOCON_FUNC0 0
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#define IOCON_FUNC1 1
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#define IOCON_FUNC2 2
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#define IOCON_FUNC3 3
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#define IOCON_FUNC4 4
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#define IOCON_FUNC5 5
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#define IOCON_MODE_INACT (0 << 3) /* No pull resistor. */
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#define IOCON_MODE_PULLDOWN (1 << 3) /* Enable pull-down resistor. */
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#define IOCON_MODE_PULLUP (2 << 3) /* Enable Pull-up resistor. */
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#define IOCON_MODE_REPEATER (3 << 3) /* Repeater mode. */
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#define IOCON_HYS_EN (1 << 5) /* Enable hysteresis. */
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#define IOCON_INV_EN (1 << 6) /* Invert input polarity. */
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/* Only for analog pins. */
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#define IOCON_ADMODE_EN (0 << 7) /* Enable analog input mode. */
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#define IOCON_DIGMODE_EN (1 << 7) /* Enable digital I/O mode. */
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#define IOCON_FILTR_DIS (1 << 8) /* Disable noise filtering. */
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/* Only for open-drain pins (I2C). */
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#define IOCON_SFI2C_EN (0 << 8) /* I2C standard mode / Fast-mode. */
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#define IOCON_STDI2C_EN (1 << 8) /* GPIO functionality. */
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#define IOCON_FASTI2C_EN (2 << 8) /* I2C Fast-mode Plus. */
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#define IOCON_OPENDRAIN_EN (1 << 10) /* Enable open-drain mode. */
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/*
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* The digital filter mode allows to discard input pulses shorter than
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* 1, 2 or 3 clock cycles.
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*/
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#define IOCON_S_MODE_0CLK (0 << 11) /* No input filter. */
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#define IOCON_S_MODE_1CLK (1 << 11)
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#define IOCON_S_MODE_2CLK (2 << 11)
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#define IOCON_S_MODE_3CLK (3 << 11)
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/*
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* Clock divisor.
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*/
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#define IOCON_CLKDIV0 (0 << 13)
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#define IOCON_CLKDIV1 (1 << 13)
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#define IOCON_CLKDIV2 (2 << 13)
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#define IOCON_CLKDIV3 (3 << 13)
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#define IOCON_CLKDIV4 (4 << 13)
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#define IOCON_CLKDIV5 (5 << 13)
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#define IOCON_CLKDIV6 (6 << 13)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LPC11U6X_PINCTRL_H_ */
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