85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/*
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* Copyright (c) 2018 Alexander Wachter
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef ZEPHYR_DRIVERS_CAN_STM32_CAN_H_
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#define ZEPHYR_DRIVERS_CAN_STM32_CAN_H_
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#include <drivers/can.h>
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#define DEV_DATA(dev) ((struct can_stm32_data *const)(dev)->data)
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#define DEV_CFG(dev) \
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((const struct can_stm32_config *const)(dev)->config)
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#define BIT_SEG_LENGTH(cfg) ((cfg)->prop_ts1 + (cfg)->ts2 + 1)
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#define CAN_NUMBER_OF_FILTER_BANKS (14)
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#define CAN_MAX_NUMBER_OF_FILTERS (CAN_NUMBER_OF_FILTER_BANKS * 4)
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#define CAN_FIRX_STD_IDE_POS (3U)
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#define CAN_FIRX_STD_RTR_POS (4U)
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#define CAN_FIRX_STD_ID_POS (5U)
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#define CAN_FIRX_EXT_IDE_POS (2U)
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#define CAN_FIRX_EXT_RTR_POS (1U)
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#define CAN_FIRX_EXT_STD_ID_POS (21U)
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#define CAN_FIRX_EXT_EXT_ID_POS (3U)
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#define CAN_BANK_IS_EMPTY(usage, bank_nr) (((usage >> ((bank_nr) * 4)) & 0x0F) == 0x0F)
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#define CAN_BANK_IN_LIST_MODE(can, bank) ((can)->FM1R & (1U << (bank)))
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#define CAN_BANK_IN_32BIT_MODE(can, bank) ((can)->FS1R & (1U << (bank)))
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#define CAN_IN_16BIT_LIST_MODE(can, bank) (CAN_BANK_IN_LIST_MODE(can, bank) && \
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!CAN_BANK_IN_32BIT_MODE(can, bank))
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#define CAN_IN_16BIT_MASK_MODE(can, bank) (!CAN_BANK_IN_LIST_MODE(can, bank) && \
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!CAN_BANK_IN_32BIT_MODE(can, bank))
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#define CAN_IN_32BIT_LIST_MODE(can, bank) (CAN_BANK_IN_LIST_MODE(can, bank) && \
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CAN_BANK_IN_32BIT_MODE(can, bank))
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#define CAN_IN_32BIT_MASK_MODE(can, bank) (!CAN_BANK_IN_LIST_MODE(can, bank) && \
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CAN_BANK_IN_32BIT_MODE(can, bank))
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struct can_mailbox {
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can_tx_callback_t tx_callback;
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void *callback_arg;
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struct k_sem tx_int_sem;
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uint32_t error_flags;
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};
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/* number = FSCx | FMBx */
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enum can_filter_type {
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CAN_FILTER_STANDARD_MASKED = 0,
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CAN_FILTER_STANDARD = 1,
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CAN_FILTER_EXTENDED_MASKED = 2,
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CAN_FILTER_EXTENDED = 3
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};
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struct can_stm32_data {
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struct k_mutex inst_mutex;
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struct k_sem tx_int_sem;
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struct can_mailbox mb0;
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struct can_mailbox mb1;
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struct can_mailbox mb2;
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uint64_t filter_usage;
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can_rx_callback_t rx_cb[CONFIG_CAN_MAX_FILTER];
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void *cb_arg[CONFIG_CAN_MAX_FILTER];
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can_state_change_isr_t state_change_isr;
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};
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struct can_stm32_config {
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CAN_TypeDef *can; /*!< CAN Registers*/
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CAN_TypeDef *master_can; /*!< CAN Registers for shared filter */
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uint32_t bus_speed;
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uint16_t sample_point;
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uint8_t sjw;
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uint8_t prop_ts1;
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uint8_t ts2;
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struct stm32_pclken pclken;
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void (*config_irq)(CAN_TypeDef *can);
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const struct soc_gpio_pinctrl *pinctrl;
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size_t pinctrl_len;
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};
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#endif /*ZEPHYR_DRIVERS_CAN_STM32_CAN_H_*/
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