83 lines
1.2 KiB
Plaintext
83 lines
1.2 KiB
Plaintext
#
|
|
# Kconfig - Apollo Lake SoC configuration options
|
|
#
|
|
# Copyright (c) 2018 Intel Corporation
|
|
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
|
#
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
#
|
|
|
|
if SOC_APOLLO_LAKE
|
|
|
|
config SOC
|
|
default "apollo_lake"
|
|
|
|
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
|
default 150000000 if LOAPIC_TIMER
|
|
default 25000000 if HPET_TIMER
|
|
|
|
config CLFLUSH_DETECT
|
|
default y if CACHE_FLUSHING
|
|
|
|
if UART_NS16550
|
|
|
|
config UART_NS16550_PCI
|
|
default y if PCI
|
|
|
|
config UART_NS16550_PORT_0
|
|
default y
|
|
|
|
if UART_NS16550_PORT_0
|
|
|
|
config UART_NS16550_PORT_0_OPTIONS
|
|
default 0
|
|
|
|
config UART_NS16550_PORT_0_PCI
|
|
default y if PCI
|
|
|
|
endif # UART_NS16550_PORT_0
|
|
|
|
config UART_NS16550_PORT_1
|
|
default y
|
|
|
|
if UART_NS16550_PORT_1
|
|
|
|
config UART_NS16550_PORT_1_OPTIONS
|
|
default 0
|
|
|
|
config UART_NS16550_PORT_1_PCI
|
|
default y if PCI
|
|
|
|
endif # UART_NS16550_PORT_1
|
|
|
|
if UART_NS16550_PORT_2
|
|
|
|
config UART_NS16550_PORT_2_OPTIONS
|
|
default 0
|
|
|
|
config UART_NS16550_PORT_2_PCI
|
|
default y if PCI
|
|
|
|
endif # UART_NS16550_PORT_2
|
|
|
|
if UART_NS16550_PORT_3
|
|
|
|
config UART_NS16550_PORT_3_OPTIONS
|
|
default 0
|
|
|
|
config UART_NS16550_PORT_3_PCI
|
|
default y if PCI
|
|
|
|
endif # UART_NS16550_PORT_3
|
|
|
|
endif # UART_NS16550
|
|
|
|
if GPIO
|
|
|
|
config GPIO_INTEL_APL
|
|
default y
|
|
|
|
endif # GPIO
|
|
|
|
endif # SOC_APOLLO_LAKE
|