zephyr/boards/seeed/xiao_esp32s3
Lucas Tamborrino e282b0ea84 soc: esp32xx: refactor clock and RTC subsystems
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.

This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.

It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-05-27 01:37:18 -07:00
..
doc
support
Kconfig.defconfig
Kconfig.sysbuild
Kconfig.xiao_esp32s3
board.cmake
board.yml
seeed_xiao_connector.dtsi
xiao_esp32s3-pinctrl.dtsi
xiao_esp32s3_appcpu.dts soc: esp32xx: refactor clock and RTC subsystems 2024-05-27 01:37:18 -07:00
xiao_esp32s3_appcpu.yaml boards: use unique names 2024-05-13 09:45:41 +02:00
xiao_esp32s3_appcpu_defconfig
xiao_esp32s3_procpu.dts soc: esp32xx: refactor clock and RTC subsystems 2024-05-27 01:37:18 -07:00
xiao_esp32s3_procpu.yaml boards: use unique names 2024-05-13 09:45:41 +02:00
xiao_esp32s3_procpu_defconfig