zephyr/arch/xtensa/core
Anas Nashif 6e27478c3d benchmarking: remove execution benchmarking code
This code had one purpose only, feed timing information into a test and
was not used by anything else. The custom trace points unfortunatly were
not accurate and this test was delivering informatin that conflicted
with other tests we have due to placement of such trace points in the
architecture and kernel code.

For such measurements we are planning to use the tracing functionality
in a special mode that would be used for metrics without polluting the
architecture and kernel code with additional tracing and timing code.

Furthermore, much of the assembly code used had issues.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-09-05 13:28:38 -05:00
..
offsets
startup
CMakeLists.txt
atomic.S
cpu_idle.c
crt1.S
fatal.c
irq_manage.c arch: Apply dynamic IRQ API change 2020-09-02 13:48:13 +02:00
irq_offload.c isr: Normalize usage of device instance through ISR 2020-09-02 13:48:13 +02:00
window_vectors.S
xtensa-asm2-util.S benchmarking: remove execution benchmarking code 2020-09-05 13:28:38 -05:00
xtensa-asm2.c arch: Apply dynamic IRQ API change 2020-09-02 13:48:13 +02:00
xtensa_intgen.py
xtensa_intgen.tmpl